Electrical and Computer Engineering professors Donald Yeung and Ankur Srivastava were awarded a $500,000, three-year grant for their project entitled, “Developing and Applying Reuse Distance Analysis Techniques for Large-Scale Multicore Processors.” The award is being funded through the National Science Foundation’s Software and Hardware Foundations (SHF) program within the Division of Computing and Communication Foundations (CCF). Director of Computer Engineering, Donald Yeung will be the Principal Investigator.
SHF supports research addressing key challenges in computer hardware design, including, but not limited to, performance, dependability, reliability, and scalability. This project addresses concerns in multi-core and many-core architecture by exploring several research directions related to multicore reuse distance (RD) analysis for loop-based parallel programs.
First, it characterizes how Concurrent Reuse Distance and per-thread RD profiles for symmetric threads vary with processor and problem scaling. Second, it will develop techniques to predict these profile variations. Simple prediction techniques such as reference groups, as well as more sophisticated parametric and non-parametric learning approaches, are being studied. Finally, by applying the new RD analyses to explore large-scale multicore design spaces, good cache hierarchy organizations will be identified. The RD analyses will incite improvements to existing memory performance enhancement techniques such as multithreading and locality optimization.
Today, simulation is the de facto method for studying multicore cache hierarchies. But simulation is costly due to the combinatorial design spaces involved, especially as multicore processors scale to 100s of cores and 100+ MB of on-chip cache. Reuse distance (RD) analysis can help architects evaluate multicore memory performance more efficiently.
July 28, 2011