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Barua, Udayakumaran Awarded Patent for Memory Allocation

Barua, Udayakumaran Awarded Patent for Memory Allocation

Associate Professor Rajeev Barua (ECE/ISR) and Ph.D. alumnus Sumesh Udayakumaran ('06) have been awarded a patent for a new dynamic computer memory allocation methodology. The researchers were issued U.S. Patent number 7,367,024, "Compiler-driven dynamic memory allocation methodology for scratch-pad based embedded systems."

Their invention offers a highly predictable, low overhead and yet dynamic, memory allocation methodology for embedded systems with scratch-pad memory. The dynamic memory allocation methodology for global and stack data accounts for changing program requirements at runtime, has no software-caching tags, requires no run-time checks, and has extremely low overheads. The methodology also yields 100% predictable memory access times.

For more information, visit the U.S. Patent Office website.

June 6, 2008


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