Faculty Directory

Vishkin, Uzi

Vishkin, Uzi

Professor
Electrical and Computer Engineering
UMIACS
5216 Iribe Center
Website(s):


EDUCATION

 

  • B.Sc. in Mathematics from the Hebrew University in Jerusalem, Israel, 1974
  • M.Sc in Mathematics from the Hebrew University in Jerusaleme, Israel,1975
  • D.Sc. in Computer Science from the Tecnion--Israel Institute of Technology in Haifa, Israel,1981

 

BACKGROUND

 

Uzi Vishkin is a professor in the Department of Electrical and Computer Engineering at The University of Maryland, College Park and at the University of Maryland Institute for Advanced Computer Studies (UMIACS). He was a postdoctoral fellow at IBM T.J. Watson Research Center in 1981-2 and on the faculty of the Courant Institute, NYU, first full time and later part-time, from 1982 to 1988. From 1984 to 1997 he was on the faculty of Tel Aviv University, Israel, where he was Chair of Computer Science in 1987-8 and Professor of Computer Science since 1988. He was Professor of Computer Science at the Technion in 2000-2001. He has been at the University of Maryland since 1988.
 
He has served on the editorial board of ACM Transactions on Algorithms and Parallel Processing Letters, was on the editorial board IEEE Transactions on Computers and is the Program Chair for the 18 th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA). He has authored, or co-authored more than 130 publications. He was elected Fellow of the ACM in 1996 and is on the ISI list of most cited researchers in Computer Science. 

 

HONORS AND AWARDS

 

    •    Maryland Daily Record Innovator of the Year Award (2007)

    •    ACM Fellow (1996)

    •    Editorial Board, ACM Transactions on Algorithms and Parallel Processing Letters

    •    Editorial Board, IEEE Transactions on Computers

    •    ISI Most Cited Researchers in Computer Science

 

PROFESSIONAL MEMBERSHIPS

 

  • Fellow of the ACM

 

Parallelism in computing Parallel algorithmics The interplay between parallel computer systems (thread-level and processor-level parallelism) and algorithms (parallel and serial) Is PRAM algorithmics implementable? A PRAM-On-Chip Vision... Design and analysis of algorithms Parallel computer architecture. The premise that inspired his work in the 2000s on the PRAM-On-Chip framework has been: Were the architecture component of PRAM-On-Chip feasible in the 1990s, its parallel programming component would have become the mainstream standard. In 1979 Uzi Vishkin identified the issue of parallel algorithms/programmability as the most critical component in developing a successful general-purpose parallel computer architecture. It simply did not look practical to proceed with building parallel computers before establishing a first satisfactory draft of its specifications. Such "specs" had to include how to think about programming the computer to be built. Many, including Uzi Vishkin, spent the next 15-20 years on parallel algorithmics. In fact, during the 1980s and the early 1990s, quite a few very talented computer science researchers worked on the following wider problem: Seek the "ultimate" parallel programming model that will allow easy expression of parallel algorithms and their programs in the model, as well as validation of the model by algorithmic paradigms and solutions for as many problems as possible. In this fierce "battle of ideas", the one approach that has beaten all its competitors by a truly wide margin was the PRAM approach. As early as 1988, standard algorithms textbooks started including significant chapters on PRAM algorithms, and as the above premise suggests, PRAM algorithms were on their way to become standard computer science know-how that every computer science graduate must command and the basis for standard parallel programming. However, multi-chip multi-processing architectures provided the only form of multi-processing available in the 1990s. They required high coordination overhead, which prevented PRAM algorithms from providing an effective abstraction for them. As a result, it became common wisdom that "PRAM algorithms are unrealistics", leading later editions of some textbooks to remove their PRAM chapters. The good news are that the PRAM-On-Chip effort is finally establishing that it is becoming feasible to build a parallel computer that can be effectively programmed by a PRAM-like language. From a 2005 perspective, the prospects for making the PRAM approach a standard for parallel algorithms and programming look pretty good: (i) "Darwin has already spoken" - see the natural selection that already happened in what was called above the battle of ideas, and (ii) The inclusion of significant PRAM chapters in standard textbooks, before concerns about implementability prevailed; but these concernes are becoming irrelevant as the PRAM-On-Chip progresses. The optimistic tone above should not hide the fact that a significant research effort is still underway. Pattern matching Theory of computing. In fact, the theory-driven PRAM-On-Chip effort aspires to provide a nice example where a forward looking theory-driven approach has practical impact. 

Professor Uzi Vishkin Featured in Communications of the ACM Magazine

Counterpoint article debates model of computation for multicore computer processors

Professor Vishkin elected to Chair ACM SPAA Steering Committee

Vishkin's term as Steering Committee Chair will be from 2020-2024.

Alumnus Yossi Matias Receives ACM’s Kanellakis Award

Matias and his colleagues pioneered a framework for algorithmic treatment of streaming massive datasets.

Vishkin’s desktop supercomputer 11 years later: Over 750 parallel programmers at a single high school and more

Vishkin's collaboration with local high school on parallel programming curriculum using XMT heads into its 11th year. 

Vishkin To Give Invited Talk on Parallel Computing at Indiana University

Vishkin's talk, "Single-Threaded Parallel Programming for Multi-Threaded Many-Core Design," is part of Indiana’s SICE CS Colloquium Series.

Vishkin, Barua and Ghanim Introduce ICE to Eliminate Programmer’s Multi-Threading – A Productivity-Buster in Parallel Computing

Intermediate Concurrent Execution (ICE) enables tightly-synchronous threading-free programming for multi-threaded execution.

ECE Announces Computer Engineering Minor

Curriculum fills a void regarding hardware and software knowledge that crossed the Clark School’s engineering curriculum.

Vishkin Offers Fresh Perspective on Commodity Computing in ACM Viewpoint

Viewpoint article challenges current standards in parallel computing.

Vishkin Awarded Two New Patents

Professor Vishkin was recently awarded patents for serial, parallel, and multi-threaded computing systems.

Vishkin’s Supercomputer Enables Ph.D.-Level Parallel Programming in High School

Vishkin collaborates with local high school teacher on parallel programming curriculum using XMT.