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Ph.D. Dissertation Defense: Hsiang-Huang Wu
Thursday, November 29, 2012
4:15 a.m.
Room 2328, AVW Bldg.
For More Information:
Maria Hoo
301 405 3681
mch@umd.edu

ANNOUNCEMENT: Ph.D. Dissertation Defense

Name: Hsiang-Huang Wu

Committee:

Professor Shuvra S. Bhattacharyya, Chair/Advisor

Professor Manoj Franklin

Professor Andrew Harris

Professor Jeffery Hollingsworth

Professor Alan Sussman, Dean's Representative

Date/Time: Thursday, November 29, 2012 at 4:15 PM

Location: Room 2328, AV Williams Building

Title: Modeling and Mapping of Optimized Schedules for Embedded Signal Processing Systems

The demand for digital signal processing (DSP) in the embedded systems has been increasing rapidly due to the proliferation of multimedia- and communication-intensive devices such as pervasive tablets and smart phones. Efficient implementation of embedded DSP systems

requires integration of diverse hardware and software components, as well as dynamic workload distribution across heterogeneous computational resources. The former implies increased complexity of application modeling and analysis, but also brings enhanced potential for achieving

improved energy consumption, cost or performance. The latter results from the increased use of dynamic behavior in embedded DSP applications. Furthermore, parallel programming is highly relevant in many embedded DSP areas due to the development and use of Multiprocessor System-On-Chip (MPSoC) technology. The need for efficient cooperation among different devices supporting diverse parallel embedded computations motivates high-level modeling that expresses dynamic signal processing behaviors and supports efficient task scheduling and

hardware mapping.

Starting with dynamic modeling, this thesis develops a systematic design methodology that supports functional simulation and hardware mapping of dynamic reconfiguration based on Parameterized Synchronous Dataflow (PSDF) graphs. By building on the DIF (Dataflow Interchange Format), which is a design language and associated software package for enveloping and experimenting with dataflow-based design techniques for signal processing systems, we have developed a novel tool for functional simulation of PSDF specifications. Thissimulation tool allows designers to model applications in PSDF and simulate thei functionality,

including use of the dynamic parameter reconfiguration capabilities offered by PSDF. With the help of this simulation tool, our design methodology helps to map PSDF specifications into efficient implementations on field programmable gate arrays (FPGAs). Furthermore, valid

schedules can be derived from the PSDF models at runtime to adapt hardware configurations

based on changing data characteristics or operational requirements. Under certain conditions,

efficient quasi-static schedules can be applied to reduce overhead and enhance predictability in

the scheduling process.

Motivated by the fact that scheduling is critical to performance and to efficient use of dynamic

reconfiguration, we have focused on a methodology for schedule design, which complements the

emphasis on automated schedule construction in the existing literature on dataflow-based design

and implementation. In particular, we have proposed a dataflow-based schedule design

framework called the dataflow schedule graph (DSG), which provides a graphical framework for

schedule construction based on dataflow semantics, and can also be used as an intermediate

representation target for automated schedule generation. Our approach to applying the DSG in

this thesis emphasizes schedule construction as a design process rather than an outcome of the

synthesis process. Our approach employs dataflow graphs for representing both application

models and schedules that are derived from them. By providing a dataflow-integrated framework

for unambiguously representing, analyzing, manipulating, and interchanging schedules, the DSG

facilitates effective codesign of dataflow-based application models and schedules for execution of

these models.

As multicore processors are deployed in an increasing variety of embedded systems, effective

utilization of multiprocessor system-on-chip (MPSoC) technology becomes critical to developing

effective embedded implementations. One of the major challenges in efficient MPSoC design

methodologies is the development of programming models that are both intuitive to designers

and efficient in mapping applications into optimized multi-core implementations. In the later part

of this thesis, we propose a new parallel programming model that addresses this challenge by

building on the methodology of DSP-oriented dataflow graphs. In particular, we incorporate into

dataflow programming novel capabilities for integrating the specification of dataflow graph

schedules, and dynamic dataflow behavior. The resulting new integrated dataflow programming

approach provides designers with an intuitive approach to specifying and exposing concurrency

in DSP applications, while also providing control in how this concurrency is exploited, flexibility in

experimenting with alternative scheduling strategies, and expressive power to represent a wide

range of applications. In addition to enhancing support for optimizing concurrent execution, our

proposed programming model naturally incorporates considerations for memory management,

data consistency, and synchronization. To demonstrate our new design and implementation

methods for MPSoC systems, we present a case study involving the mapping of a background

subtraction application onto a state-of-the-art multicore programmable digital signal processor

platform.

This Event is For: Graduate • Faculty

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