Ph.D. Dissertation Defense: Devanarayanan Perinthatta Ettisserry

Monday, July 27, 2015
2:00 p.m.
AVW 2168
Maria Hoo
301 405 3681
mch@umd.edu

ANNOUNCEMENT:  Ph.D. Dissertation Defense

 

Name: Devanarayanan Perinthatta Ettisserry

Committee:

Prof. Neil Goldsman, Chair/Advisor

Prof. Agisilaos Iliadis

Prof. Jeremy Munday

Prof. Martin Peckerar

Prof. Lourdes G. Salamanca-Riba, Dean's representative

 

Date/Time: Monday, 27 July, 2015 at 2:00 PM


 Location: AV Williams 2168

 

Title: Integrated modeling of reliability and performance of 4H-Silicon Carbide MOSFETs using atomistic and device simulations.

 

Abstract:

            4H-Silicon Carbide (4H-SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a promising technology that could revolutionize future high-temperature and high-power electronics industry. However, poor device reliability and channel mobility (performance) that stem from the inferior quality of 4H-Silicon Carbide-Silicon dioxide (4H-SiC/SiO2) interface have kept it from realizing its full potential. This dissertation investigates the role of interfacial and near-interfacial atomic defects as the root cause of these key concerns. It also proposes device processing strategies that could mitigate reliability-limiting defects for improved next-generation 4H-SiC power MOSFETs.

In order to understand the atomic nature of material defects, and their manifestations in electrical measurements, this work employs an integrated modeling approach together with experiments. In this approach, the electrical activity of defects, and their physical behavior are analyzed using first-principles hybrid Density Functional Theory (DFT), which solves the many-body Schrodinger equation of quantum mechanics. The insights from first-principles calculations are integrated with conventional physics-based modeling techniques like the Drift-Diffusion and Rate equation simulations to model device characteristics like I-V curves and threshold voltage instability transients. Subsequently, the atomic-level models, developed using this approach, are validated by comparison with electrical measurements.

From the device reliability perspective, this dissertation firstly models the recently observed excessive time-dependent worsening of threshold voltage (Vth) instability in 4H-SiC MOSFETs operated under High-Temperature and Gate-Bias (HTGB) conditions. In this context, the first-principles calculations revealed a category of ‘electrically inactive’ oxygen vacancies, which could be structurally transformed under HTGB stress to form electrically active switching oxide hole traps. Subsequently, the transients of this Arrhenius hole trap activation process was modeled, with activation barriers derived with the help of a hybrid DFT-based Nudged Elastic Band (NEB) method. The calculated time-evolution of the buildup of positively charged vacancies correlated very well with the experimentally measured time-dependence of Vth instability. This agreement helps to validate the atomic-level oxygen vacancy hole trap activation model for HTGB-induced Vth instability that is developed in this dissertation.

Secondly, this work designates near-interfacial single carbon interstitial defect in silicon dioxide as an additional switching oxide hole trap that causes room-temperature device threshold voltage instability. The most stable defect configuration – called the carboxyl structure – is determined to be thermodynamically stable in its neutral and doubly positive charge states, with charging-related structural transformations similar to that of oxygen vacancy hole traps. Stability-providing bonding mechanisms in carboxyl hole traps are also discussed.

Thirdly, this work uses first-principles molecular dynamics simulations to develop device processing strategies that could mitigate reliability-limiting defects in 4H-SiC power MOSFETs. It identifies Fluorine treatment to be very effective in neutralizing oxygen vacancy and carboxyl hole traps, unlike molecular hydrogen treatment. Similarly, controlled Nitric Oxide (NO) passivation is proposed to eliminate carboxyl defects.

From the device performance perspective, this dissertation proposes a novel methodology to identify and quantify mobility-limiting defects at the interface by integrating Drift-Diffusion simulations of a 4H-SiC power MOSFET with DFT. This methodology resolves the density of interface trap (Dit) spectrum into contributions from three atomically distinct defects. Among them, carbon di-interstitial defect in 4H-SiC side of the interface is identified to be the key mobility-limiting trap in 4H-SiC MOSFETs using hybrid DFT.
 

Audience: Graduate  Faculty 

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