ENEE 759M: Advanced Topics in Computer Engineering: Microarchitecture

List of Papers

Below are papers/talk slides to be studied for this course.

Go to Topic:

• Hardware Trends and Challenges.
• Program Criticality.
• Helper Threads.
• Multi-Core Architectures.
• Low Power.
• Reliability.
• Quantum Computing.

Hardware Trends and Challenges

• New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies
  F. Pollack
  Keynote Speech, 32nd International Symposium on Microarchitecture (MICRO-32), 1999.
  

• The Future Evolution of High-Performance Microprocessors
  N. Jouppi
  Keynote Speech, 38th International Symposium on Microarchitecture (MICRO-38), 2005.
  

• Micro-Architectural Innovations: Boosting Processor Performance Beyond Technology Scaling
  Andreas Moshovos and G. S. Sohi
  Proceedings of the IEEE, vol. 89, no. 11, November 2001.

Program Criticality

• Computing Along the Critical Path
  D. Tullsen and B. Calder
  UC San Diego Technical Report, October 1998.
  

• Quantifying Instruction Criticality
  E. Tune, D. Tullsen, and B. Calder
  11th International Conference on Parallel Architectures and Compilation Techniques, September 2002
  

• Dynamic Dead-Instruction Detection and Elimination
  J. Adam Butts and G.S. Sohi
  10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), Oct 2002.
  

• A Criticality Analysis of Clustering in Superscalar Processors (Micro 2005)
  P. Salverda and C. Zilles
  International Symposium on Microarchitecture, 2005.
  

Helper Threads

• Understanding the Backward Slices of Performance Degrading Instructions
  Craig B. Zilles and Gurindar S. Sohi
  27th International Symposium on Computer Architecture (ISCA-27), 2000.
  Abstract

• Dynamic Speculative Precomputation
  Jamison D. Collins, Dean M. Tullsen, Hong Wang, John P. Shen
  34th International Symposium on Microarchitecture (MICRO-34), Dec 2001.
  

• Slipstream Processors: Improving both Performance and Fault Tolerance
  K. Sundaramoorthy, Z. Purser, and E. Rotenberg
  9th International Conference on Architectural Support for Programming Languages and Operating Systems, November 2000.
  

• Speculative Data-Driven Multithreading
  Amir Roth and G. S. Sohi
  Seventh International Symposium on High-Performance Computer Architecture (HPCA-7), Jan. 2001.
  

• Master/Slave Speculative Parallelization
  Craig Zilles and G.S. Sohi
  35th International Symposium on Microarchitecture (MICRO-35), Nov. 2002.
  

Multi-Core Architectures

• Speculative Multithreaded Processors (PDF)
  G. S. Sohi and Amir Roth
  Int. Conf. on High Performance Computing (HiPC), December 2000
  

• Speculative Multithreaded Processors
  G. S. Sohi and Amir Roth
  IEEE Computer, vol. 34, no. 4, April 2001.

• A Single-Chip Multiprocessor
  L. Hammond, B. A. Nayfeh, and K. Olukotun
  IEEE Computer, September 1997.

• Chip Multithreading: Opportunities and Challenges
  L. Spracklen and S. Abraham
  HPCA-11. February 2005.

• Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
  R. Kumar, V. Zyuban, and D. M. Tullsen
  International Symposium on Computer Architecture, 2005.

• Conditional Memory Ordering
  C. Praun, T. Cain, J-d Choi, and K. Ryu
  International Symposium on Computer Architecture, 2006.

Low Power

• Power: A First-Class Architectural Design Constraint
  T. N. Mudge
  IEEE Computer, pp. 52-58, April 2001.
  

• Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors
  D. Brooks, et al
  IEEE Micro, Nov/Dec 2000.
  

• Exploring the Potential of Architecture-Level Power Optimizations
  John S. Seng and Dean M. Tullsen
  3rd International Workshop on Power-Aware Computer Systems, December 2003.
  

• Reducing Power with Dynamic Critical Path Information
  John S. Seng, Eric S. Tune, Dean M. Tullsen
  34th International Symposium on Microarchitecture (MICRO-34), Dec 2001.
  

• Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines
  E. Talpes and D. Marculescu
  International Symposium on Computer Architecture, 2005.
  

• Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
  R. Balasubramonian, N. Muralimanohar, K. Ramani, and V. Venkatachalapathy
  11th International Symposium on High-Performance Computer Architecture (HPCA-11), Feb 2005.
  

• Dynamically Trading Frequency for Complexity in a GALS Microprocessor
  S. Dropsho, G. Semeraro, D. H. Albonesi, G. Magklis, and M. L. Scott
  nnual IEEE/ACM International Symposium on Microarchitecture, 2004
  

• Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
  Y. Li, K. Skadron, Z. Hu, and D. Brooks
  11th International Symposium on High Performance Computer Architecture (HPCA), Feb. 2005.
  

• Using Performance Counters for Runtime Temperature Sensing in High-Performance Processors
  K.-J. Lee and K. Skadron
  Workshop on High-Performance, Power-Aware Computing (HP-PAC), in conjunction with the International Parallel and Distributed Processing Symposium, April 2005.
  

Reliability

• The Impact of Technology Scaling on Lifetime Reliability
  Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, and Jude A. Rivers
  International Conference on Dependable Systems and Networks (DSN '04) June 2004.
  

• A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
  Shubhendu S. Mukherjee, Christopher Weaver, Joel Emer, Steven K. Reinhardt, and Todd Austin
  36th Annual International Symposium on Microarchitecture (MICRO-36), December 2003.
  

• DIVA: A Dynamic Approach to Microprocessor Verification
  Todd Austin
  Journal of Instruction Level Parallelism, May 2000.
  

• Efficient Checker Processor Design
  Saugata Chatterjee, Chris Weaver, and Todd Austin
  33rd International Symposium on Microarchitecture (MICRO-33), December 2000.
  

• Dual Use of Superscalar Datapath for Transient-Fault Detection and Recovery
  Joydeep Ray, James C. Hoe, and Babak Falsafi
  Tech Report, CMU, June 2001.
  

• Fingerprinting: Bounding Soft-Error Detection Latency and Bandwidth
  Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, and Andreas G. Nowatzyk
  International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XI), October 2004.
  

• Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
  Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Toan Pham, Rajeev Rao, Conrad Ziesler, David Blaauw, Todd Austin, Trevor Mudge, and Krisztián Flautner
  36th Annual International Symposium on Microarchitecture (MICRO-36), December 2003.
  

• Making Typical Silicon Matter with Razor
  Todd Austin, David Blaauw, Trevor Mudge, and Krisztián Flautner
  IEEE Computer, March 2004.
  

Quantum Computing

• The Quantum Computer: An Introduction
  Jacob West
  
• Quantum Computing: How the weird logic of the subatomic world could make it possible for machines to calculate millions of times faster than they do today
  Lov K. Grover
  
  This page last modified by Manoj Franklin on 26-January-2006 02:08 EST