Final Exam
ENEE244-010x: Digital Logic Design
Fall 2015 Final Exam Info
The Final Exam will be held on Wednesday, Dec. 16 from 1:30-3:30pm in EGR 1108. It will consist of 9 problems (some with multiple parts). The exam is **cumulative** and will cover material from the entire semester, with emphasis on material since the last exam (Lectures 16-24).
Here are a list of topics from Lectures 16-24 **only** (i.e. only the new material is listed, but the exam will cover all material from Lectures 1-24):
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Programmable Logic Devices: PLD Notation, PROM, PLA, PAL.
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Flip-Flops: The Basic Bistable Element, Latches, SR Latch, SR-complement Latch,
Latch, Gated SR Latch, Gated D Latch, Timing Considerations, Propagation Delays,
Minimum Pulse Width, Setup and Hold times, Master-Slave Flip-Flops, Master-Slave
SR Flip-Flop, Master-Slave JK Flip-Flop, 0's and 1's Catching, Edge-Triggered
Flip-Flops, Edge-Triggered D-Flip-Flop, Negative-Edge Triggered D Flip Flops,
Positive edge triggered T flip-flop, Characteristic Equations, Registers, Counters.
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Structure and operation of clocked synchronous sequential networks: Current state, next state, Mealy versus Moore.
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Analysis of clocked synchronous sequential networks: Excitation and output expressions, transition equations, transition tables, excitation tables, state tables, state diagrams.
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Modeling clocked synchronous sequential behavior: Constructing state diagrams from a description of the functionality of the network.
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State table reduction: Determining equivalent pairs of states, obtaining the equivalence classes of states, constructing a minimal state table.
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The state assignment problem: Simple guidelines for obtaining state assignments, state-assignment map, unused states.
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Completing the design of clocked synchronous sequential networks: Application tables, transition table to excitation table, using K-maps for final circuit design, realizations using programmable logic devices.
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Note the exam WILL NOT include material on ASMs or ASM Charts.
What will be given to you on the final:
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Sheet with Boolean Algebra Postulates and Theorems
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Symbolic representation of MSI components if needed for a logic
design using MSI components problem.
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Examples of PROM/PLA/PAL structures as necessary
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Diagrams of flip-flops/latches as necessary but only for
in-depth questions (such as timing diagram questions).
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Rules I, II, III for the state assignment problem.
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Application tables as needed for problems that ask you to convert
transition tables to excitation tables.