Note that the parametric cells like transistors and taps are now appearing as distinct cells in your library. This is because they have been packed into the gds file like all the higher-level cells during the stream-out process, as the tapeout does not assume that the foundry has any prior information as to the structure of, say, an NMOS, before the lithography is done.|
This is why it is important to use a hierarchical system as much as possible while doing layout. If, for instance, instead of using the different cells nand1 and inv1 to make up the and1 cell, which we then placed into our top-level cell andchip, instead of two instances of nmos and two of pmos (because we have two different sizes for n-channel transistors and for p-channel transistors each) we would have three instances in the readback. If we had put in two AND gates that way, transistor-by-transistor in the top level cell, we would have ten transistor instances, while properly using two instances of the and1 cell for that purpose results in four total transistor instances again. Now imagine a chip with hundreds of gates and thousands of transistors. The output file size would increase unmanageably.