- A full DRC. You should have noted down the type and number of errors the padframe by itself gives when put through a DRC, so make sure there aren't any extra errors appearing once you've put your layout in the padframe.
- An extraction and visual checking of your important networks: VDD, ground, input, output. The and chip we've designed in the example so far has, respectively, the vdd, ground, one input and the output networks highlighted in the following pictures:
(Do zoom in and make sure that the highlit parts in the gate-scale are the proper sections.) - While viewing the extracted networks, make sure that unrelated pads aren't shorted to each other, and especially vdd and ground aren't shorted. Also, if your circuit (as is very likely) contains transistors, make sure all the ptaps are connected to ground and all the ntaps are connected to VDD (See Part 6 to review about the taps).
Remember that what we really have here is a hierarchy of cells: The top-level cell, called andchip in this example, is composed of two lower-level cells, zframe05 and and1, plus some extra metal layer rectangles to provide connections . and1 itself has two lower-level cells, nand1 and inv1.
The tapeout process is, essentially, packing this hierarchical structure into a single file that includes the hierarchy information within. We can create such packed files in a variety of formats. MOSIS accepts two formats: .gds ("Stream") and .cif . They prefer the .gds format, so we will use this format.
- Library Name: The name of the library that the top-level cell is in (here, the library which the full chip layout andchip is in, i.e. demo1).
- Top Cell Name: The name of the full chip layout (here, andchip).
- Output: This indicates the output format. We need this to be marked as Stream DB.
- Output File: The name of the tapeout stream file we choose. Should have a .gds extension (Example: andchipout.gds).
- Scale UU/DBU: Since we did layout in units of microns, this number should remain at 0.0010000 and the unit indicator should remain indicating micron.
- Error Message File: This is a filename for the log file we want Cadence to create as it is performing the tapeout. The default filename will be PIPO.LOG, but it's a good idea to customize this to different names for different tapeouts (and later, for exporting the designs back in).
* Warning * (poIlHooksLayerNumMap) - Cannot get the stream layer rule of (layer=238, purpose=239) |
This is about a layer that appears in the default layermap file, but that our technology does not use. We can safely ignore similar warnings given for "layer 220" and "layer 230".
List Hierarchy (#cellInst,#arrayInst)
--------------------------------------------------------------------------
andchip layout
.zframe05 layout(1)
..padfc layout(4)
..padvdd layout(1)
...padbox layout(1)
....padboxx layout(289)
..padgnd layout(1)
...padbox layout(1)
....padboxx layout(289)
..padaref layout(38)
...padbox layout(1)
....padboxx layout(289)
.and1 layout(1)
..nand1 layout(1)
...pmos$$31830060 layout(2)
...nmos$$31831084 layout(1)
...ntap$$31204396 layout(1)
...ptap$$31832108 layout(1)
..inv1 layout(1)
...ptap$$31832108 layout(1)
...nmos$$31200300 layout(1)
...pmos$$31202348 layout(1)
...ntap$$31204396 layout(1)
.m2_m1$$31208492 layout(59)
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This is a representation of the hierarchical structure of your design, with the top cell being listed at the head of the list and the number of dots present in front of each cell name showing the depth of that cell in the hierarchy. Also note that parametrical cells, like those for the transistors and taps, are tagged with identification numbers.
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Note that the parametric cells like transistors and taps are now appearing as distinct cells in your library. This is because they have been packed into the gds file like all the higher-level cells during the stream-out process, as the tapeout does not assume that the foundry has any prior information as to the structure of, say, an NMOS, before the lithography is done. This is why it is important to use a hierarchical system as much as possible while doing layout. If, for instance, instead of using the different cells nand1 and inv1 to make up the and1 cell, which we then placed into our top-level cell andchip, instead of two instances of nmos and two of pmos (because we have two different sizes for n-channel transistors and for p-channel transistors each) we would have three instances in the readback. If we had put in two AND gates that way, transistor-by-transistor in the top level cell, we would have ten transistor instances, while properly using two instances of the and1 cell for that purpose results in four total transistor instances again. Now imagine a chip with hundreds of gates and thousands of transistors. The output file size would increase unmanageably. |
- Zoom in to a single via or contact and measure its dimensions to make sure they are two lambda by two lambda (0.6x0.6 microns in this technology). This verifies that the scaling went correctly.
- Select and descend into the different cells as low as you can go to make sure everything is there.
- If you wish, run extraction again and double-check connections.
If everything went well, your .gds file is ready for submission to MOSIS. The exact procedure for submission depends on your project and under which program you are intending to fabricate your chip.