Doing Layout With Cadence
Extraction and Simulation
- Extraction is the process through which Cadence extracts the underlying circuit from a layout. The program recognizes transistors, some parasitic capacitances, and which points are electrically connected together. It can also extract diodes if the dio_id layer is used. (It should be able to extract resistors and capacitors as well, but the author of this tutorial has never tried this.)
- On the Layout window, use the menu Verify -> Extract.... The Extractor dialogue window will come up. Make sure that the rules library is correct. The Rules file should be "divaEXT.rul" and the Extract Method should be "flat", both set by default. Hit the "Set Switches" button and select the options "Extract_parasitic_caps" and "Keep_labels_in_extracted_view" using the CTRL key adn the left mouse button. These should now appear in the Switch Names box. Click OK to start the extraction and observe its progress in the icfb main window.
- On the Library Manager window, we can now see that there is a fourth cellview created for the cell nand1: "extracted". Doubleclick this view name to open the extracted version. If you move the mouse pointer over the newly opened window, you'll see electrical networks being highlighted, and clicking on any point in such a net will create a bold outline for all the network:
- By zooming in around the extracted view, you can find the MOS transistors and parasitic capacitances it extracted. Now we need to compare the extracted netlist with the schematic. Use the menu Verify -> LVS... for the Layout-vs.-Schematic check. The LVS dialogue box will come up. A second window titled Form Contents Different may also come up, if you had done an LVS check in this directory before. In this window, always choose Form Contents ("form" here refers to the LVS window) and click "OK". In the LVS window, make sure that the library, cell and views to be compared are correct. The Rules library should again be our technology library, and the rules file is divaLVS.rul, both set by default. Click "Run" to start the run and watch the progress from the main icfb window. If a Save Cellviews dialogue box comes up, click "OK" for the LVS to proceed (Virtuoso treats the extraction we just did from the layout cellview as a update to the file and so asks if we want to save it, for instance).
- Once the LVS is done running, it's going to pop up a window titled Analysis Job Succeeded that says something like "Job '/homes/username/directoryname/LVS' that was started at 'begintime' has succeeded". This only means that the LVS job ran without crashing. It doesn't mean that the layout-vs-schematic comparison found no errors. On this window, click "OK", and go to the LVS window to ask for the output report by clicking on the Output button. A window will appear, displaying the output file. (In the figure below, we've scrolled down a bit to make the errors visible)
- The layout shows "8 nets" while the schematic was found to have "6 nets", because the pmos/nmos devices we used in the schematic have their bodies tied to vdd/ground by default, but not those in the layout. So the layout has the active areas of the transistors floating, and they show up as two extra nets in the netlist. To fix this, we have to add an ntap (to connect the nwell of the PMOS transistors to vdd) and a ptap (to connect the bodies of the NMOS transistors to ground) to the layout and redo the extraction and LVS check.
- Close the LVS output window, LVS dialogue box, and the extracted view. In the Library Manager, select the extracted view of your cell nand1 and use the menu Edit -> Delete to get rid of this old extraction. The Delete CellViews window that comes up already has the correct configuration (as below), just click "OK".
- In the Layout Editor, hit i to add an instance, click Browse in the Create Instance window and find the ntap in the NCSU_TechLib_ami06 library in the Library Browser that comes up. Place it so as to touch the nwell area of one of the PMOS transistors. Then find the ptap and place it next to the NMOS transistors. Then connect the metal1 connectors of these elements to VDD and ground rails, respectively:
- Save the layout, do a DRC, and (assuming no design rule violations) do extraction again. the extracted cellview reappears in the Library Manager. Open this view and click on the vdd and ground nets to verify yourself the bodies of the transistors are correctly connected, and then use the menu Verify -> LVS again to do the LVS check. Remember to choose "Form Contents" in the Form Contents Different dialogue box and click Output on the LVS dialogue box to see the result of the check after the job is completed:
- This time our laid-out circuit is what we intended to design. To simulate this including the parasitic effects caused by our layout, close the LVS window, the LVS output window, the layout, schematic and the extracted views of the nand1 cell to get rid of the clutter a bit. Reopen the schematic view of your testcirc cell, which included the test circuit.
- One thing you can experiment with from this schematic is to descend into the lowest hierarchical design levels, since this schematic contains a lower level cell---your nand1 cell is embedded in this circuit design. Click on the nand1 symbol to select it, and hit x (or use the menu Design -> Hierarchy -> Descend Read...) to bring up the Descend dialogue box. The drop-down menu allows you to bring up whichever cellview you want; choose "layout" as an example and click OK:
- The layout of your cell nand1 will come up. Note that you cannot edit this view from here, since you chose "Descend Read" (Hitting shift-x or choosing Descend Edit... would disable this read-only mode). To go back to the higher level (in this case, the schematic cellview of the cell testcirc) hit b or use the menu Design -> Hierarchy -> Return.
- Use the menu Tools -> Analog Environment to bring up the Affirma window for simulation. Change the simulator to SpectreS as described here.
- Use the Setup -> Environment menu in the Affirma window to bring up the Environment Options window. Note that the dialogue box for the Switch View List initially says "spectreS spice cmos_sch cmos.sch schematic veriloga ahdl". This is a list of views the simulator looks at to see where a model for the circuit netlist is available; the first one it finds it's going to stop and simulate. Before the word "schematic," add the word "extracted". Click OK to go back to the Affirma window.
- Set up the transient analysis, choose the outputs to be plotted, and run the simulation as described here. The outputs will once again be plotted automatically. The circuit is again operating properly:
- Zooming in to measure, say, the fall time and t_PHL of this simulation and comparing it with the same measurement of the results of the schematic view simulation, we can see the effect of the added parasitic capacitances. The first picture is the output of the extracted view simulation, where t_fall=357.876 ps and t_PHL=233.92 ps ; the second picture is the output of the schematic simulation, with t_fall=326.72 ps and t_PHL=231.957 ps.
On to Part 7: Bringing cells together.
Back to the Cadence Demo Index.
Last modified: Mon Oct 6 20:17:44 EDT 2003