Caleb Serafy

HOME RESEARCH PUBLICATIONS EDUCATION MY GROUP

Dept. of ECE
University of Maryland
College Park, MD

Office: AVW 1313
Phone: 301-405-0283
Email: cserafy1@umd.edu

This is me with my wife Kacee, our daughter Celestina, and our puppy Priscilla. UPDATE: Our second daughter was born 2/10/16, picture coming soon

2013-Present: Architectural-Physical Co-Design of 3D CPUs with Micro-Fluidic Cooling

Stacking ICs vertically and interconnecting them with through silicon (i.e. vertical) vias (TSVs) allows a designer to significantly reduce the interconnect delay and power consumption in a circuit, as well as facilitating higher transistor density independent of technology node.  Moreover, 3D stacking can integrate chips from disparate manufacturing technologies, such as memory, logic, MEMS, analog/RF and optical/chemical sensors. TSVs can provide massive bandwidth between such heterogeneously integrated chips, and facilitate new System on Chip (SoC) architectures that were suboptimal or infeasible in traditional 2D designs. Although there are many great improvements 3D integration can bring, some non-trivial challenges must first be overcome to much this technology viable.

Cooling
Vertically stacking chips significantly increases the power density on the chip, requiring new cooling schemes such as micro-fluidic cooling to remove the heat. In addition to higher power density, the heat generated in the intermediate layers of a 3D stack are trapped between the insolating materials that separate chip layers, and cannot be removed with a traditional air cooling interface on the top layer of the stack. 3D ICs will require a more aggressive cooling solution that can scale with the number of layers in a stack in order to unlock the true potential of this technology. When more aggressive cooling is applied to 3D ICs, possibilities for new aggressive computer architectures become achievable. Our research has shown a 2x improvement in performance and a 1.5x improvement to energy efficiency by co-designing 3D CPUs with micro-fluidic cooling. This work has been published in [C4],[C5], [C6], [C8] and presented in [P1].

Co-design
Although micro-fluidic cooling can offer substantial thermal improvements, there are many other aspects of a 3D design that must be optimized to find truly optimal design points. Moreover, there exists many interdependencies between different aspects of a design. For example, the design of micro-fluidic heatsink not only affects the cooling capacity, but can also constraint the placement and density of TSVs [C4],[C10],[J3]. Thermal profile is also significantly affected by physical design aspects such as floorplaning, and there often exists a tradeoff between performance and temperature  [J2]. Thus we argue that a comprehensive co-design paradigm is needed for 3D ICs with micro-fluidic cooling, which simultaneously optimizes architectural design, physical design and heatsink design.

3D CPU Architectural Design Space Exploration and Modeling
Three-dimensional integration significantly expands the CPU architectural design space. Exhaustive simulation and optimization of all design points is computationally infeasible. We propose to use spline modeling techniques to estimate design properties (e.g. performance, power, energy efficiency, temperature, delay and area) of unsimulated architectural design points. Preliminary data shows the ability to identify design points within 0.5% of optimal while reducing number of simulations 23x compared to exhaustive simulation. This work is ongoing and currently under review in a top tier conference.

Acknowledgements
This work was funded by the DARPA IceCool project and NSF grant CCF1302375.

2011-2013: 3D IC Transient and Hard Fault Resilience

Signal Integrity
Traditional models of wire coupling cannot be directly extended to TSVs because TSVs are suspended in the silicon substrate itself, whereas traditional 2D wires are suspended in a layer of thick oxide. TSVs are also much thicker than 2D wires due to manufacturing requirements on aspect ratio, and the thickness of the silicon substrate. For these reasons, new models of TSV coupling are needed, and techniques for mitigating TSV coupling must be developed. In [C11], [J5], we developed a geometric model of TSV coupling and propose an algorithm for shield insertion as a method for reduction of coupling. In [C7], [J4] we integrate our shield insertion algorithm into a force directed TSV/standard cell placement algorithm which is coupling aware.

Manufacturing
Vertical integration introduces new steps to the manufacturing process which has the effect of significantly reducing yield.  The process of growing the TSV is prone to open and sort circuit defects.  The stacking process is prone to misalignment errors where TSVs on adjacent layers belonging to the same net don't match up and thus are unconnected, or when two TSVs on adjacent layers belong to different nets accidentally touch and become connected. Moreover, TSVs suffer from ageing effects such as electromigration and cracking due to thermal cycling in different ways than traditional 2D wires due to large stress gradients surrounding TSVs. TSV redundancy and reconfigurability is the standard method for repairing manufacturing faults at the foundry. The research published in [C9] investigates the possibility of extending these schemes to also repair runtime faults due to circuit aging as well, by proposing a method of tracking TSV health over time and deciding when to retire an ageing TSV and replace it with a spare.

Acknowledgements
This work was funded by NSF grant CCF1302375.

Journal Publications (Accepted/Published):

[J1] Y. Xie, C. Bao, C. Serafy, T. Lu, A. Srivastava and M. Tehranipoor. Security and Vulnerability Implications of 3D ICs. In IEEE Transactions on Multi-Scale Computing Systems, 2016. [link]

[J2] C. Serafy, Z. Yang, Y. Hu, A. Srivastava and Y. Joshi. Thermo-Electric Codesign of 3D CPUs and Embedded Micro-fluidic Pin-fin Heatsinks. In IEEE Design and Test, 2015. [link]

[J3] C. Serafy, A. Srivastava and D. Yeung. Unlocking the True Potential of 3D CPUs with Micro-Fluidic Cooling. In IEEE Transactions on VLSI, 2015. [link]

[J4] C. Serafy and A. Srivastava. TSV Placement and Shield Insertion for TSV-TSV Coupling Reduction in 3-D Global Placement. In IEEE Transactions on CAD: Special Issue on Physical Design Techniques for Advanced Technology Nodes, 2015. [link]

[J5] C. Serafy, B. Shi, and A. Srivastava. A Geometric Approach to Chip-Scale TSV Shield Placement for the Reduction of TSV Coupling in 3D-ICs. In Integration, the VLSI Journal: VLSI for the New Era. Elsevier, 2014. [link]

Journal Publications (Under Review):

[R1] T. Lu, C. Serafy, Z. Yang, S.K. Lim and A. Srivastava. 3D ICs: Design Methods and Tools. In IEEE Transactions on CAD, 2016.

Conference Publications:

[C1] T. Lu, C. Serafy, Z. Yang and A. Srivastava. Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUs. In IEEE International Symposium on Low Power Electronics and Design 2016 (ISLPED'16). IEEE, 2016.

[C2] Z. Yang, C. Serafy and A. Srivastava. ECO Based Placement and Routing Framework for 3D FPGAs with Micro-fluidic Cooling. In IEEE International Symposium on Field-Programmable Custom Computing Machines  2016 (FCCM'16). IEEE, 2016.

[C3] C. Serafy, T. Lu and A. Srivastava. Thermal-Reliability Physical Co-Optimization During Architectural Design Space Exploration of 3D-CPUs. In Proceedings of the Government Microcircuit Applications and Critical Technology Conference  2016 (GOMACTech'16). 2016.

[C4] C. Serafy, A. Srivastava, A. Bar-Cohen and D. Yeung. Design Space Exploration of 3D CPUs and Micro-Fluidic Heatsinks with Thermo-Electrical-Physical Co-Optimization. In Proceedings of the ASME International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems 2015 (InterPACK'15). ASME, 2015. [link]

[C5] C. Serafy, A. Srivastava and D. Yeung. Unlocking the True Potential of 3D CPUs with Micro-Fluidic Cooling. In Proceedings of the IEEE International Symposium on Lower Power Electronics and Design 2014 (ISLPED'14). IEEE, 2014. [link]

[C6] C. Serafy, A. Srivastava and D. Yeung. Continued Frequency Scaling in 3D ICs through Micro-Fluidic Cooling. In Proceedings of the IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems 2014 (ITherm'14). IEEE, 2014. [link]

[C7] C. Serafy and A. Srivastava. Coupling-Aware Force Driven Placement of TSVs and Shields in 3D-IC layouts. In Proceedings of the ACM International Symposium on Physical Design 2014 (ISPD'14). ACM, 2014. [link]

[C8] C. Serafy, B. Shi, A. Srivastava and D. Yeung. High Performance 3D Stacked DRAM Processor Architectures with Micro-Fluidic Cooling. In Proceedings of the IEEE 3D System Integration Conference 2013 (3DIC'13). IEEE, 2013. [link]

[C9] C. Serafy and A. Srivastava. Online TSV Health Monitoring and Built-in Self-Repair to Overcome Aging. In Proceedings of the 15th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'13). IEEE, 2013. [link]

[C10] B. Shi, C. Serafy, and A. Srivastava. Co-Optimization of TSV Assignment and Micro-Channel Placement for 3D-ICs. In Proceedings of the 23rd ACM International Conference on Great lakes Symposium on VLSI (GLSVLSI'13). ACM, 2013. [link]

[C11] C. Serafy, B. Shi, and A. Srivastava. Geometric Approach to Chip-Scale TSV Shield Placement for the Reduction of TSV Coupling in 3D-ICs. In Proceedings of the 23rd ACM International Conference on Great lakes Symposium on VLSI (GLSVLSI'13). ACM, 2013. [link]

Magazine Articles:

[M1] C. Serafy and A. Srivastava. Leakage Power: Physical Mechanisms and Possible Solutions. In Electronics Cooling, December 2014. [link]

Poster Presentation:

[P1] C. Serafy, B. Shi, A. Srivastava and D. Yeung. Electro-Thermal Co-Design for Micro-Fluidically Cooled 3D ICs. At the 51st Design Automation Conference (DAC'14).

Last Updated: 5/11/2016