Caleb Serafy

HOME RESEARCH PUBLICATIONS EDUCATION MY GROUP

Dept. of ECE
University of Maryland
College Park, MD

Office: AVW 1313
Phone: 301-405-0283
Email: cserafy1@umd.edu

This is me with my wife Kacee, our daughter Celestina, and our puppy Priscilla. UPDATE: Our second daughter was born 2/10/16, picture coming soon

Journal Publications (Accepted/Published):

[J1] Y. Xie, C. Bao, C. Serafy, T. Lu, A. Srivastava and M. Tehranipoor. Security and Vulnerability Implications of 3D ICs. In IEEE Transactions on Multi-Scale Computing Systems, 2016. [link]

[J2] C. Serafy, Z. Yang, Y. Hu, A. Srivastava and Y. Joshi. Thermo-Electric Codesign of 3D CPUs and Embedded Micro-fluidic Pin-fin Heatsinks. In IEEE Design and Test, 2015. [link]

[J3] C. Serafy, A. Srivastava and D. Yeung. Unlocking the True Potential of 3D CPUs with Micro-Fluidic Cooling. In IEEE Transactions on VLSI, 2015. [link]

[J4] C. Serafy and A. Srivastava. TSV Placement and Shield Insertion for TSV-TSV Coupling Reduction in 3-D Global Placement. In IEEE Transactions on CAD: Special Issue on Physical Design Techniques for Advanced Technology Nodes, 2015. [link]

[J5] C. Serafy, B. Shi, and A. Srivastava. A Geometric Approach to Chip-Scale TSV Shield Placement for the Reduction of TSV Coupling in 3D-ICs. In Integration, the VLSI Journal: VLSI for the New Era. Elsevier, 2014. [link]

Journal Publications (Under Review):

[R1] T. Lu, C. Serafy, Z. Yang, S.K. Lim and A. Srivastava. 3D ICs: Design Methods and Tools. In IEEE Transactions on CAD, 2016.

Conference Publications:

[C1] T. Lu, C. Serafy, Z. Yang and A. Srivastava. Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUs. In IEEE International Symposium on Low Power Electronics and Design 2016 (ISLPED'16). IEEE, 2016.

[C2] Z. Yang, C. Serafy and A. Srivastava. ECO Based Placement and Routing Framework for 3D FPGAs with Micro-fluidic Cooling. In IEEE International Symposium on Field-Programmable Custom Computing Machines  2016 (FCCM'16). IEEE, 2016.

[C3] C. Serafy, T. Lu and A. Srivastava. Thermal-Reliability Physical Co-Optimization During Architectural Design Space Exploration of 3D-CPUs. In Proceedings of the Government Microcircuit Applications and Critical Technology Conference  2016 (GOMACTech'16). 2016.

[C4] C. Serafy, A. Srivastava, A. Bar-Cohen and D. Yeung. Design Space Exploration of 3D CPUs and Micro-Fluidic Heatsinks with Thermo-Electrical-Physical Co-Optimization. In Proceedings of the ASME International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems 2015 (InterPACK'15). ASME, 2015. [link]

[C5] C. Serafy, A. Srivastava and D. Yeung. Unlocking the True Potential of 3D CPUs with Micro-Fluidic Cooling. In Proceedings of the IEEE International Symposium on Lower Power Electronics and Design 2014 (ISLPED'14). IEEE, 2014. [link]

[C6] C. Serafy, A. Srivastava and D. Yeung. Continued Frequency Scaling in 3D ICs through Micro-Fluidic Cooling. In Proceedings of the IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems 2014 (ITherm'14). IEEE, 2014. [link]

[C7] C. Serafy and A. Srivastava. Coupling-Aware Force Driven Placement of TSVs and Shields in 3D-IC layouts. In Proceedings of the ACM International Symposium on Physical Design 2014 (ISPD'14). ACM, 2014. [link]

[C8] C. Serafy, B. Shi, A. Srivastava and D. Yeung. High Performance 3D Stacked DRAM Processor Architectures with Micro-Fluidic Cooling. In Proceedings of the IEEE 3D System Integration Conference 2013 (3DIC'13). IEEE, 2013. [link]

[C9] C. Serafy and A. Srivastava. Online TSV Health Monitoring and Built-in Self-Repair to Overcome Aging. In Proceedings of the 15th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'13). IEEE, 2013. [link]

[C10] B. Shi, C. Serafy, and A. Srivastava. Co-Optimization of TSV Assignment and Micro-Channel Placement for 3D-ICs. In Proceedings of the 23rd ACM International Conference on Great lakes Symposium on VLSI (GLSVLSI'13). ACM, 2013. [link]

[C11] C. Serafy, B. Shi, and A. Srivastava. Geometric Approach to Chip-Scale TSV Shield Placement for the Reduction of TSV Coupling in 3D-ICs. In Proceedings of the 23rd ACM International Conference on Great lakes Symposium on VLSI (GLSVLSI'13). ACM, 2013. [link]

Magazine Articles:

[M1] C. Serafy and A. Srivastava. Leakage Power: Physical Mechanisms and Possible Solutions. In Electronics Cooling, December 2014. [link]

Poster Presentation:

[P1] C. Serafy, B. Shi, A. Srivastava and D. Yeung. Electro-Thermal Co-Design for Micro-Fluidically Cooled 3D ICs. At the 51st Design Automation Conference (DAC'14).

Last Updated: 5/11/2016