University of Maryland
Brought to you by The Memory-Systems Research Consortium
Overview: Spring 2007The memory system in any computer is very complex, comprised of several interacting subsystems, themselves quite complex; subsystems include DRAMs, disks, caches, and their controllers and busses, each available in many possible configurations. The memory system is where all important information is stored; as such, it is critical that the memory system be robust, efficient, and responsive. Modern computers are limited by the memory system to a significant degree: for instance, the performance of supercomputers from Cray and IBM is entirely determined by memory (Cray observes that an increase in sustained memory bandwidth of 20% results in an increase in system performance of 20%, whereas significant increases in processor speed have only negligible impact on system performance).
The complexity of modern memory subsystems and the resulting memory system has recently become a significant problem. To achieve higher performance, modern subsystems incorporate intelligence in the form of transaction scheduling and local caching of data, and a wide range of configuration parameters is available for design and implementation at all levels of the system. We have shown that the interactions between these intelligent subsystems and design parameters is both complex and extremely detrimental; for instance, we have identified "systemic" behaviors that are non-intuitive, caused by unexpected interactions between otherwise independent subsystems, and responsible for order-of-magnitude shifts in performance and cost. These are behaviors only detectable through extremely detailed modeling of the system, a holistic approach to design.
Our work presents a framework in which to study memory systems in a holistic fashion; today, it has become necessary to consider circuit-level ramifications of system-level design decisions and, as well, to consider system-level ramifications of circuit-level design decisions. Considering the system at such a level of detail allows one to dramatically improve both the cost and the performance of the system, and it also guarantees that a chosen design will not fall prey to overlooked details, such as system level assumptions that violate circuit-level requirements.
Our recent research investigates different facets of the memory system to a significant level of detail. We have developed a highly detailed model of the memory controller and DRAM subsystem; a full-system model that incorporates detailed performance and power models of caches, DRAMs, and disks and captures both application and operating-system activity; circuit-level models of popular low-power SRAM designs to study leakage characteristics, power/performance trade-offs, and noise susceptibility; a lightweight simulator that captures and measures all memory activity out to several trillion instructions, without sampling; and a set of data-mining applications that significantly stresses the memory system. We have studied the memory system from many different perspectives, including the circuit level (e.g., power studies of pipelined nanometer caches at the 90nm, 65nm, 45nm and 32nm technology nodes; the noise susceptibility of low-power SRAMs; etc.), the device-architecture level (e.g., DDR3 and DDR4 device-level parameter studies done on behalf of JEDEC 42.3), and the system level (e.g., power and performance studies of the upcoming Fully Buffered DIMM architecture; memory-scheduling for power-limited high-performance DDR3 devices; application behavior beyond 10 billion instructions; characterization of bioinformatics workloads; etc.). It is our ultimate goal to significantly transform the way memory-system design is done.
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Contact InformationProf. Bruce Jacob - - http://www.ece.umd.edu/~blj/
Traditional correspondence can be sent to
Prof. Bruce Jacob
Dept. of Electrical & Computer Engineering
University of Maryland
College Park, MD 20742