The Studies

2015	IEEE CAL	"The 2 PetaFLOP, 3 Petabyte, 9 TB/s, 90 kW Cabinet: A System Architecture for Exascale and Big Data." Bruce Jacob. IEEE Computer Architecture Letters, published on-line June 2015. DOI 10.1109/LCA.2015.2451652.
		Our vision for what a next-generation exascale-class computing system should look like: a large network of journaled non-volatile, NAND-flash, main-memory nodes.
	IEEE CAL	"The case for VLIW-CMP as a building block for Exascale." Bruce Jacob. IEEE Computer Architecture Letters, published on-line April 2015. DOI 10.1109/LCA.2015.2424699.
		Our vision for what a next-generation exascale-class compute node should look like.
2013	HPCA	"Technology comparison for Large Last-Level Caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM." Mu-Tien Chang, Paul Rosenfeld, Shih-Lien Lu, and Bruce Jacob. Proc. 19th International Symposium on High Performance Computer Architecture (HPCA 2013), pp. 143-154. Shenzhen, China, February 2013.
		One of the hallmarks of large-scale systems is large last-level caches, and it is surprising what the trade-offs look like -- you end up choosing technologies you would not have expected.
	ITJ	"An integrated simulation infrastructure for the entire memory hierarchy: Cache, DRAM, nonvolatile memory, and disk." J. Stevens, P. Tschirhart, M.-T. Chang, I. Bhati, P. Enns, J. Greensky, Z. Chishti, S.-L. Lu, and B. Jacob. Intel Technology Journal, vol. 17, no. 1. 2013.
		This describes the simulation environment for our non-volatile main memory systems.
2012	[HMC]	"Peering over the memory wall: Design space and performance analysis of the Hybrid Memory Cube." Paul Rosenfeld, Elliott Cooper-Balis, Todd Farrell, Dave Resnick, and Bruce Jacob. University of Maryland Systems and Computer Architecture Group Technical Report UMD-SCA-2012-10-01. October 2012 (one reference added 2013).
		This describes our work for Micron during their development of the Hybrid Memory Cube DRAM. Paul and Elliott did the performance modeling for several years. When Micron announced the DRAM in 2012, we were finally able to write up what we had done. This is the part we can talk about. :)
	ISCA	"Buffer On Board memory systems." Elliott Cooper-Balis, Paul Rosenfeld, and Bruce Jacob. Proc. 39th International Symposium on Computer Architecture (ISCA 2012), pp. 392-403. Portland OR, June 2012.
		A whole lot of high-performance servers use this architecture today ... it has become one of the staples in high-capacity memory design.
2010	[NVMM]	"A journaled, NAND-flash main-memory system." B. Jacob, I. Bhati, M.-T. Chang, P. Rosenfeld, J. Stevens, P. Tschirhart, Z. Chishti, S.-L. Lu, J. Ang, D. Resnick, and A. Rodrigues. University of Maryland Systems and Computer Architecture Group Technical Report UMD-SCA-2010-12-01. December 2010 (some references updated 2014).
		This is what next-generation memory systems are going to look like.
2009	MoBS	"CMP memory modeling: How much does accuracy matter?" S. Srinivasan, L. Zhao, B. Ganesh, B. Jacob, M. Espig, and R. Iyer. Proc. Fifth Annual Workshop on Modeling, Benchmarking and Simulation (MoBS), pp. 24-33. Austin TX, June 2009.
		We started looking at CMP issues a long time ago ...
	Morgan Claypool book	The Memory System: You Can't Avoid It; You Can't Ignore It; You Can't Fake It. Bruce Jacob, with contributions by Sadagopan Srinivasan and David T. Wang. ISBN 978-1598295870. Morgan & Claypool Publishers, June 2009.
		Since 2008 (when I had finished writing this book and it was being sent around to reviewers) we have been telling people that the main memory needs to be made out of flash instead of DRAM.
2008	TECS	"Accurate and fast system-level power modeling: An XScale-based case study." A. Varma, E. Debes, I. Kozintsev, P. Klein, and B. Jacob. ACM Transactions on Embedded Computing Systems, vol. 7, no. 4, pp. 25:1-20. April 2008.
		Being able to simulate large systems means you have to be able to simulate things extremely fast.
2007	(book)	Memory Systems: Cache, DRAM, Disk. Bruce Jacob, Spencer W. Ng, and David T. Wang, with contributions by Samuel Rodriguez. ISBN 978-0-12-379751-3. Morgan Kaufmann Publishers, Fall 2007.
		This represents the culmination of much of our work in memory systems. Currently sitting at about 1000 pages, densely set (~500 words per page), it is roughly half a million total words.
	HPCA	"Fully-Buffered DIMM memory architectures: Understanding mechanisms, overheads and scaling." Brinda Ganesh, Aamer Jaleel, David Wang, and Bruce Jacob. Proc. 13th International Symposium on High Performance Computer Architecture (HPCA 2007). Phoenix AZ, February 2007.
		This is the first published peer-reviewed study of the performance of FB-DIMM. Up until this point, the only study publicly available anywhere was a master's thesis (also from our group) by Rami Nasr.
2006	ISLPED	"Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)." Samuel V. Rodriguez and Bruce Jacob. Proc. International Symposium on Low Power Electronics and Design (ISLPED 2006), pp. 25-30. Tegernsee Germany, October 2006.
		This is the most accurate study of SRAM energy & power yet; Sam's software, vCACTI, is a major overhaul of existing CACTI-based programs. Read his thesis.
	HPCA	"Last-level cache (LLC) performance of data-mining workloads on a CMP--A case study of parallel bioinformatics workloads." Aamer Jaleel, Matthew Mattina, and Bruce Jacob. Proc. 12th International Symposium on High Performance Computer Architecture (HPCA 2006), pp. 88-98. Austin TX, February 2006.
		Few besides Aamer are really looking at what sort of sharing patterns exist in the last-level cache.
2005	HPCA	"Using Virtual Load/Store Queues (VLSQs) to reduce the negative effects of reordered memory instructions." Aamer Jaleel and Bruce Jacob. Proc. 11th International Symposium on High Performance Computer Architecture (HPCA 2005), pp. 191-200. San Francisco CA, February 2005.
		The funny thing about out-of-order execution is that it is great for general instructions, but it is sucky for memory instructions. Norm Jouppi was one of the first to notice this, and Aamer was his intern at the time ... Norm handed the idea off to Aamer, and the study was born. Took us several years to get people to believe the results.
	ISPASS	"BioBench: A benchmark suite of bioinformatics applications." K. Albayraktaroglu, A. Jaleel, X. Wu, M. Franklin, B. Jacob, C.-W. Tseng, and D. Yeung. Proc. 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2005), pp. 2-9. Austin TX, March 2005.
		A really cool set of benchmarks that pounds the memory system.
	SIGARCH	"DRAMsim: A memory-system simulator." David Wang, Brinda Ganesh, Nuengwong Tuaycharoen, Katie Baynes, Aamer Jaleel, and Bruce Jacob. SIGARCH Computer Architecture News, vol. 33, no. 4, pp. 100-107. September 2005.
		Simply put, the most accurate DRAM system simulator in the world. At least, that we know of.
2004	ISCA	"Extended Split-Issue: Enabling flexibility in the hardware implementation of NUAL VLIW DSPs." Bharath Iyer, Sadagopan Srinivasan, and Bruce Jacob. Proc. 31st International Symposium on Computer Architecture (ISCA 2004), pp. 364-375. Munchen, Germany, June 2004.
		We started looking at VLIW issues a long time ago ...
2003	IEEE Micro	"A case for studying DRAM issues at the system level." Bruce Jacob. IEEE Micro, vol. 23, no. 4, pp. 44-56. July/August 2003.
		This is really the publication that got us into supercomputer design. Because of this paper, researchers at Cray reached out to us; and so we designed their Black Widow memory controller. Then we were invited to start participating in DOE supercomputer design processes. Later, like the work for Cray, Micron reached out to us to help them design the Hybrid Memory Cube.

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