The RiSC-16 Architecture
The RiSC-16 is a teaching instruction-set used by the author at the University of Maryland, and which is a blatant (but sanctioned) rip-off of the Little Computer (LC-896) developed by Peter Chen at the University of Michigan. The primary differences include the following:
RiSC stands for Ridiculously Simple Computer, which makes sense in the context in which the instruction-set is normally used -- to teach simple organization and architecture to undergraduates who do not yet know how computers work. The architecture has a whopping 8 opcodes, uses 8 registers, and is nonetheless general enough to execute fairly sophisticated programs. This makes it a relatively useful teaching tool, as it allows students to look at computer architecture concepts from simple to advanced without the instruction-set getting in the way or cluttering up the picture.
This page includes documentation on the instruction set and several different processor implementations, including sequential, pipelined, and out-of-order. Verilog for the out-of-order core is also available for download. Verilog for the other implementations is not available, because those are projects that I assign to my architecture students.
PDF Documents:
File Name | Document Name | Document Description |
RiSC-isa.pdf | The RiSC-16 Instruction-Set Architecture | Describes the instruction-set architecture: machine-code forms, assembly-code forms, etc. |
RiSC-sys.pdf | RiSC-16 System Architecture | Describes the system-level component of the instruction set, including system calls, exceptions, how interrupts should be handled, etc. STILL IN DEVELOPMENT. |
RiSC-seq.pdf | RiSC-16: Sequential Implementation | Describes a sequential implementation of the architecture: control flow, data flow, etc. |
RiSC-pipe.pdf | The Pipelined RiSC-16 | Describes a pipelined implementation of the architecture: control flow, data flow, pipeline stages, pipeline hazards, data forwarding, etc. |
RiSC-oo.1.pdf | An Out-of-Order RiSC-16: Tomasulo + Reorder Buffer = Interruptible Out-of-Order | Describes an out-of-order implementation: instruction queue (ROB/RUU), fetch buffers, forwarding logic, wakeup/scheduling logic, recovery from branch misspeculations, memory request queue, commit logic, etc. Version 1 does not implement precise interrupts (sorry; I ran out of time). Version 2 will have TLBs with software-managed TLB-refill (a la MIPS). |
RiSC-ex.pdf | RiSC-oo.1.v Execution Example | The document An Out-of-Order RiSC-16 gives the first dozen machine cycles in the execution of a small assembly-code file. The full execution is given in this document. |
Source Code:
File Name | Description of Contents |
a.c | C code for a rudimentary RiSC-16 assembler. |
laplace.s | RiSC-16 assembly code for a decent-sized benchmark, written by Vince Weaver and Asher Lazarus -- former enee350 and enee759m students. |
If you do not find what you are looking for, please feel free to email me with suggestions for more/different/modified documents. Same goes for bug fixes.