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ENEE359V Advanced Digital Design with HDL

Course Description: The course covers concepts of designing, modeling, simulating, and synthesizing digital systems using the Verilog hardware description language. It introduces the flow of designing advanced digital systems at different abstraction levels. Introduces the industry-adopted styles for modeling in terms of synthesis to ASIC standard-cell libraries and FPGAs, and on how to model testing environments for functional verification and debug. The Verilog language is taught through various concrete examples of advanced digital modules, such as ALUs, Multipliers (Booth), Dividers, FIFOs, etc., culminating with a simple RISC microprocessor. The class is taught in a laboratory setting and all the design and language concepts are introduced and exercised through a series of implementation projects using an FPGA board, culminating into a term project that develops a systems of significant complexity.

Prerequisite(s): ENEE244

Corequisite(s): None

Course Objectives:

  • Learn the fundamentals of the Verilog hardware description language
  • Understand the structural, register-transfer (RTL), and algorithmic levels of abstraction for modeling digital hardware systems
  • Design and modeling of combinational and sequential digital systems (Finite State Machines)
  • Understand and apply the architecture of controller - datapath in designing advanced systems, such as FIFOs, Booth multiplier, and micro-processors
  • Understand and apply the concept of test-benches to create testing behavioral environments for simulation based verification
  • Learn the fundamentals of RTL synthesis
  • Learn to use simulation and synthesis EDA software for FPGA-based systems

Topics Covered:

  • Basic Verilog Language Structures (Datatypes, Modules, etc.)
  • Structural and Behavioral Specifications (Basic gates, User-defined primitives, Modeling levels, Synthesizable operations, Continuous assignments)
  • Simulation. Testbenches and debugging.
  • Finite State Machine Specifications and Styles
  • Algorithmic State Machine (ASM) and Datapath (ASMD) Charts
  • Synthesis flow. Synthesis to Standard cells and FPGA
  • Design Reuse - Instantiation of parametrized modules
  • Improving Timing, Area, and Power – Pipelining, Gating, and Delay calculations
  • FPGA architectures and FPGA-based designs