VLSI Design Automation Under Fabrication Variability
Prof. Ankur Srivastava
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| Dr. Ankur Srivastava |
Today’s IC design is facing several challenges due to increasing circuit complexity and decreasing feature size, as it pushes to extend Moore’s law into nano-scale dimensions. Apart from the direct challenges that arise as a result of feature scaling, such as increasing leakage power and reliability issues, imperfections in the manufacturing process for deca-nanometer dimensions have recently become a major design hurdle. Manufacturing variability deviates the parameters of the devices and interconnects from their designed values, and consequently varies the performance metrics of a design.
From an IC design automation perspective, a shift in paradigm, from deterministic to probabilistic, is needed to handle the random nature of fabrication variability. Such a probabilistic paradigm should accurately model different varying parameters, such as leakage power or circuit delay, and well capture their correlations due to common sources of variations or physical location on the chip. Moreover probabilistic design optimization under fabrication variability needs to be efficient and accurate, and have an effective definition for the notion of optimality. Developing optimization techniques that provably converge to the optimal solution under fabrication variability is another important challenge in this domain.
The goal of Prof. Ankur Srivastava and his research group is to study these challenges and incorporate them in the IC design automation framework.
Prof. Srivastava's research is aimed at improving the productivity and profitability of the semiconductor industry, and improving the applicability of nanotechnology where manufacturing randomness of digital circuits is a major concern.
Prof. Srivastava is focusing on developing formal optimization schemes for synthesizing large scale digital circuits while proactively considering randomness induced yield loss as an optimization criteria.
Srivastava recently received a three-year National Science Foundation (NSF) grant for his research titled "Optimization Schemes for Large Scale Digital Circuits in Presence of Fabrication Randomness."
Srivastava was also featured in EE Times for his paper, "Variability-Driven Formulation for Simultaneous Gate Sizing and Post-Silicon Tunability Allocation," for which he earned a best paper award at the ACM International Symposium on Physical Design.
For further details please see: http://www.ece.umd.edu/~ankurs/
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