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Ph.D. Dissertation Defense: Lai-Huei Wang
Thursday, April 24, 2014
1:30 a.m.
Room 2168, AVW
For More Information:
Maria Hoo
301 405 3681
mch@umd.edu

ANNOUNCEMENT: Ph.D. Dissertation Defense

Name: Lai-Huei Wang

Committee:
Professor Shuvra S. Bhattacharyya, Chair/Advisor
Professor Manoj Franklin
Professor Steven A. Tretter
Professor K.J. Ray Liu
Professor Yang Tao, Dean's Representative

Date/Time: Thursday, April 24, 2014, 1:30 PM

Location: AV Williams building, Room 2168


Title: HIERARCHICAL MAPPING TECHNIQUES FOR SIGNAL PROCESSING SYSTEMS ON PARALLEL PLATFORMS

 
Abstract:

Dataflow models are widely used for expressing the functionality of digital
signal processing (DSP) applications due their useful features,
such as providing formal mechanisms for description of application
functionality, imposing minimal data-dependency constraints in
specifications, and exposing task and data level parallelism effectively.
Due to the increased complexity of dynamics in modern DSP applications,
dataflow-based design methodologies require significant
enhancements in modeling and scheduling techniques to provide for efficient
and flexible handling of dynamic behavior. To address this problem, in this
thesis, we propose an innovative framework for mode- and
dynamic-parameter-based modeling and scheduling. We apply, in a systematically
integrated way, the structured mode-based dataflow modeling capability of
dynamic behavior together with the features of dynamic parameter
reconfiguration and quasi-static scheduling.

Moreover, in our proposed framework, we present a new design method called
parameterized multidimensional design hierarchy mapping (PMDHM), which is
targeted to the flexible, multi-level reconfigurability, and intensive
real-time processing requirements of emerging dynamic DSP systems. The proposed
approach allows designers to systematically represent and transform multi-level
specifications of signal processing applications from a common, dataflow-based
application-level model. In addition, we propose a new technique for mapping
optimization that helps designers derive efficient, platform-specific
parameters for application-to-architecture mapping. These parameters help to
maximize system performance on state-of-the-art parallel platforms for embedded
signal processing.

To further enhance the scalability of our design representations and
implementation techniques, we present a formal method for analysis and
mapping of parameterized DSP flowgraph structures, called topological
patterns, into efficient implementations. The approach handles an
important class of parameterized schedule structures in a form that is
intuitive for representation and efficient for implementation.

We demonstrate our methods with case studies in the fields of wireless
communication and computer vision. Experimental results from these case studies
show that our approaches can be used to derive optimized implementations on
parallel platforms, and enhance trade-off analysis during design space
exploration. Furthermore, their basis in formal modeling and analysis
techniques promotes the applicability of our proposed approaches to diverse
signal processing applications and architectures.
 
 

This Event is For: Graduate • Faculty

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