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Ph.D. Dissertation Defense Ishwar Bhati
Friday, April 18, 2014
9:00 a.m.
AVW 2328
For More Information:
Maria Hoo
301 405 3681

ANNOUNCEMENT: Ph.D. Dissertation Defense

Name: Ishwar Bhati

Advisory Committee:

Professor Bruce Jacob, Chair/Advisor

Dr. Zeshan Chishti

Professor Manoj Franklin

Professor Gang Qu

Professor Pete Keleher, Dean's Representative

Date/Time: Friday, April 18 2014, 9:00 AM

Location: AV Williams building, #2328 (AVW 2328)



DRAM has been the technology choice for main memory due to its low latency and high density features. With each new technology generation, speed and density of DRAM devices have increased to meet the performance and capacity requirements of main memory. These trends have resulted in two main scalability concerns: First, the increase in device speed increases the background power consumed by DRAM peripheral circuitry. Second, the increase in device density increases the penalty of refreshing DRAMs leaking capacitive cells. Previously, the overheads of refresh have been insignificant but as the size and speed of DRAM chips continue to increase, refresh becomes a dominating factor of DRAM performance and power dissipation. The objective of this dissertation is to conduct a comprehensive study of the issues related to refresh operations in modern DRAM devices and then propose techniques to mitigate refresh penalties.

To understand the growing consequences of refresh operations, we describe various refresh command scheduling schemes; analyze the refresh modes and timings in modern commodity DRAM devices; and characterize the variations in DRAM cells’ retention time. Then, we quantify refresh penalties by varying device speed, size, timings, and total memory capacity. Further, we summarize prior refresh mechanisms and their applicability in future computing systems. Finally, based on our experiments and observations, we propose techniques to mitigate refresh energy efficiency and scalability problems.

Refresh operations not only introduce performance penalty but also pose energy overheads. In addition to energy required for refreshing, the background energy component, dissipated by DRAM peripheral circuitry and on-die DLL during refresh command, becomes significant in future devices. We propose set of techniques referred collectively as coordinated refresh, in which scheduling of low power modes and refresh commands are coordinated so that most of the required refreshes are issued when the DRAM device is in the deepest low power self-refresh (SR) mode. Our approach saves background power because the peripheral circuitry and clocks are turned off in the SR mode.

Further, we observe that as the number of rows in DRAM scales, a large body of research on refresh reduction using retention time and access awareness will be rendered ineffective. Because these mechanisms require the memory controller to have fine-grained control over which regions of the memory are refreshed, while in JEDEC DDRx devices, a refresh operation is carried out via an auto-refresh command, which refreshes multiple rows from multiple banks simultaneously. The internal implementation of auto-refresh is completely opaque outside the DRAM—all the memory controller can do is tell the DRAM to refresh itself—the DRAM handles all else, in particular determining which rows in which banks are to be refreshed. We propose a modification to the DRAM that extends its existing control-register access protocol to include the DRAMs internal refresh counter and also introduce a new dummy refresh command that skips refresh operations and simply increments the internal counter. We show that these modifications allow a memory controller to reduce as many refreshes as in prior work, while achieving significant energy and performance advantages by using auto-refresh most of the time.


This Event is For: Graduate • Faculty

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