Ph.D. Dissertation Defense: Inkeun Cho
Thursday, March 27, 2014
2:00 p.m. AVW Bldg, Room 2460
For More Information:
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ANNOUNCEMENT: Ph.D. Dissertation Defense
Committee: Advisory Committee:
Professor Shuvra S. Bhattacharyya, Chair/Advisor
Professor Martin Peckerar
Professor Neil Goldsman
Professor Manoj Franklin
Professor Patrick McCluskey, Dean's Representative
Date/Time: Thursday, March 27 2014, 2:00 PM
Location: AVW Building, Room 2460
Title: HARDWARE AND SOFTWARE ARCHITECTURES FOR ENERGY- AND RESOURCE-EFFICIENT SIGNAL PROCESSING SYSTEMS
For a large class of digital signal processing (DSP) systems, design and implementation of hardware and software is challenging due to stringent constraints on energy consumption and resource requirements. In this thesis, we develop methods to address this challenge by proposing new constraint-aware system design methods for DSP systems, and energy- and resource-optimized designs of key DSP subsystems that are relevant across various application areas. In addition to general methods for optimizing energy consumption and resource utilization, we present streamlined designs that are specialized to efficiently address platform-dependent constraints.
We focus on two specific aspects in our development of energy- and resource-optimized design techniques:
(1) Application-specific systems and architectures for energy- and resource-efficient design.
We develop application-specific techniques for optimizing two important applications related to wireless communication. First, we address challenges in efficient implementation of wireless sensor network building energy monitoring systems (WSNBEMSs). We present a new energy analysis method for estimating energy consumption in embedded sensor nodes at the application level and the network level. We then apply the proposed energy analysis method to develop new energy management schemes in order to maximize system lifetime for WSNBEMSs. Based on our techniques for modeling and energy analysis, we have implemented an optimized WSNBEMS for a real building, and validated our energy analysis techniques through measurements on this implementation. The performance of our implementation is also evaluated in terms of monitoringaccuracy and energy consumption savings. We have demonstrated that by applying the proposed scheme, system lifetime can be improved significantly without affecting monitoring accuracy.
We also present a designer-configurable, resource-efficient, field programmable gate array (FPGA) architecture for implementation of orthogonal frequency division multiplexing (OFDM) systems. Our design achieves a significant improvement in resource efficiency for a given data rate. This efficiency
improvement is achieved through careful analysis of how fast Fourier transform (FFT) computation is performed within the context of OFDM systems, and through streamlining memory management and control logic based on this analysis. In particular, our OFDM-targeted FFT design eliminates redundant buffer memory, and simplifies control logic to save FPGA resources. We have synthesized and tested our design using the Xilinx ISE 13.4 synthesis tool, and compared the results with the Xilinx FFT v7.1, which is a widely used commercial FPGA intellectual property (IP) core. We have demonstrated that our design provides at least 8.8% enhancement in terms of resource efficiency compared to Xilinx FFT v7.1 when it is embedded within the same OFDM configuration.
(2) Dataflow-based methods for structured design and implementation of energy- and resource-efficient DSP systems.
Use of dataflow graphs is a popular approach to modeling and design of DSP systems, and is used in a wide variety of development environments for DSP. In this thesis, we develop new design methods targeted to efficient application of dataflow techniques, and we demonstrate their utility in systematically addressing energy and resource constraints.
First, we introduce a dataflow-based design approach based on integrating interrupt-based signal acquisition in the context of parameterized synchronous dataflow (PSDF) modeling. This application of PSDF provides a useful foundation for structured development of power- and energy-efficient wireless sensor network systems for dynamic, data-driven applications systems (DDDASs), including DDDASs that employ intensive acquisition and processing of signals from heterogeneous sensors. To demonstrate our proposed new signal-processing-oriented, dataflow-based design approach ---which we refer to as DDPSDF (data-driven PSDF) --- we have implemented an embedded speech recognition system using the proposed DDPSDF techniques. We demonstrate that by applying our DDPSDF approach, energy- and resource-efficient embedded software can be derived systematically from high level models of DDDAS functional structure.
Also, we develop advances to the lightweight dataflow (LWDF) programming model for design and implementation of signal processing systems. LWDF is a recently-introduced programming model for applying dataflow techniques to DSP system design in a manner that is relatively easy to learn and integrate into existing design processes, and that provides agility in retargeting designs across different kinds of platforms. In this thesis, we present an in-depth development of LWDF-Verilog (LWDF-V}), which is an integration of the LWDF programming model with the Verilog hardware description language (HDL), and we demonstrate the utility of LWDF-V for design and implementation of digital systems for signal processing. We emphasize new features that we have developed in LWDF for efficient integration with HDLs, and we emphasize the application of LWDF-V to design of DSP systems with dynamic parameters on FPGA platforms. We demonstrate our proposed LWDF-V programming model and methods for managing dynamic parameters through design and implementation of actors for inner product computation.