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Ph.D. Dissertation Defense: Mu-Tien Chang
Thursday, November 14, 2013
10:00 a.m.
Room 2328, AVW Building
For More Information:
Maria Hoo
301 405 3681

ANNOUNCEMENT: Ph.D. Dissertation Defense

Name: Mu-Tien Chang


Professor Bruce Jacob, Chair/Advisor

Professor Manoj Franklin

Professor Gang Qu

Professor Donald Yeung

Professor Jeffrey Hollingsworth, Dean’s Representative

Date/Time: Thursday, November 14, 2013 at 10:00am

Location: AVW 2328

Title: Technology Implications for Large Last-Level Caches


Large last-level cache (L3C) is efficient for bridging the performance and power gap between processor and memory. Several memory technologies, including SRAM, STT-RAM (MRAM), and embedded DRAM (eDRAM), have been used or considered as the technology to implement L3Cs. However, each of them has inherent weaknesses: SRAM is relatively low density and dissipates high leakage; STT-RAM has long write latency and requires high write energy; eDRAM requires refresh. As future processors are expected to have larger last-level caches, the objective of this dissertation is to study the tradeoffs associated with using each of these technologies to implement L3Cs.

In order to make useful comparisons between L3Cs built with SRAM, STT-RAM, and eDRAM, we consider and implement several levels of details. First, to obtain unbiased cache performance and power properties (i.e., read/write access latency, read/write access energy, leakage power, refresh power, area), we prototype caches based on realistic memory and device models. Second, we present simplistic analytical models that enable us to quickly examine different memory technologies under various scenarios. Third, we review power-optimization techniques for each of the technologies, and propose using a low-cost dead-line prediction scheme for eDRAM-based L3Cs to eliminate unnecessary refreshes. Finally, the highlight of this dissertation is the comparison and analysis of low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM. We report system performance, last-level cache energy breakdown, and memory hierarchy energy breakdown, using an augmented full-system simulator with the execution of a range of workloads and input sets. From the insights gained through simulation results, STT-RAM has the highest potential to save energy in future L3C designs, whereas for contemporary processors, SRAM-based L3C results in the fastest system performance, and eDRAM consumes the lowest energy.

This Event is For: Graduate • Faculty

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