Intel Tech Talk
Thursday, October 17, 2013
5:30 p.m. 1202 Glenn L. Martin Hall
For More Information:
Engineering Co-op & Career Services
301 405 3863 CareerEngr@umd.edu http://intel.com
Moores Law - Is There Still Plenty of Room at the Bottom?
Dr. Tuyen Tran is an Engineering Technology Development Manager with Intels Portland Technology Development (PTD) Division. Since joining PTD in 1996, Dr. Tran has worked on a variety of technical projects in the development of Defect Inspection technologies, and Yield Improvement. He is currently working on the research, development and integration of State of the art Inspection, Imaging, and elemental composition analysis capability for the14nm and 10nm technologies.
Dr. Tran will discuss the history of transistor scaling at Intel, the future of Moore's Law, as well as Intel's research, development and manufacturing methodology and silicon technology leadership. His presentation will address how Intels process technologies have evolved and include discussion on Intels latest iteration of silicon technology with 14nm Tri-Gate transistors.
For more information on job opportunities visit: www.intel.com/jobs.