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Ph.D. Dissertation Defense: Babak Nouri
Thursday, December 20, 2012
10:00 a.m.
Room 2460, AVW Bldg.
For More Information:
Maria Hoo
301 405 3681

Announcement: Ph.D. Dissertation Defense

Name: Babak Nouri

Date: Thursday, December 20, 2012 at 10am

Location: AVW 2460


Professor Pamela Abshire, Chair

Professor Neil Goldsman.

Professor Timothy Horiuchi

Professor Marty Peckerar

Professor Isabel Lloyd (Dean’s Representative)

Title: Integrated Single-Photon Sensing And Processing

Platform In Standard CMOS


Advanced miniaturized optoelectronic systems will usher in the next generation of smart pixel arrays required for the high end sensing and processing microsystems such as LOC (Lab-On-a-Chip), µTAS (micro Total Analysis System) and Point of Care diagnostics. The necessary technological breakthrough,towards this purpose, is the cost effective integration of high speed single-photon optical elements with powerful signal processing and readout electronics on a

single monolithic platform.

The introduction of Single Photon Avalanche Diodes (SPADs) in standard CMOS process opened an avenue for low-cost realization of such large scale integrated optoelectronics system. However, large scale reproduction of the SPAD single pixel performance with SPAD-based focal plane arrays in conventional CMOS process has been fraught with challenges due to the presence of trade-off parameters associated with

SPAD operation at both pixel and system levels [1].

The challenge at the system level is the development

of a monolithic readout architecture that is capable

of supporting the throughput associated with the

unimpeded asynchronous traffic from a large number

of single-photon pixels. The problem is further

complicated because potential solutions are constrained

by the performance trade-offs stemming from the suboptimal optical characteristics of the CMOS process technology.

System architecture design is the primary challenge confronting research in the field. No general solution for complete system integration on a single chip currently exist with the current research and development efforts primary focused towards compromise solutions customized for specific

applications. A general solution is postponed awaiting

the advent of ultra-compact and versatile process

technologies that can alleviated some of the system

performance trade-offs involving functionality/

performance and photosensitive area. The underlying

motivation behind this research is to bridge the existing

performance gap in development of high performance

large-area SPAD arrays through the introduction of

novel design concepts and innovative implementation

schemes within the context of existing low-cost,

conventional CMOS process.

The basic adopted strategy is based on application of

novel design concepts and innovative implementation

schemes at each architectural design level from device

junction structure to smart pixel design and ultimately

array system implementation.

Towards this purpose a standard CMOS p-n junction

with structural design to yield large detection area

and high SNR performance has been proposed. The

dark noise for the proposed structure was measured

and enhancing effect of the incorporated features on

performance and fill factor has been established.

Additionally, since the SPAD operation at the pixel

level requires electronic support, a novel front-

end interface has been developed that optimizes

speed and noise performance of the device while

providing an adjustable output interface signal that can

accommodates array level operation. The operational

features of the smart pixel support and complement

system-level functional features. In order to enable

valid interpretation of pixel measurement data in

presence of system nonlinearities due to confined

processing time a theoretical detection model has been

developed and verified against controlled empirical


Finally at the array level the favorable functional

features exclusive to the digital readout architectures

and the performance advantages unique to the analog

readout scheme are simultaneously represented within

the proposed system architecture. The novel method

introduced for design and implementation of detector

output interface resolves the inherent implementational

conflicts associated with supporting concurrent digital

and analog operation at the pixel and array level

respectively. As a result the architectural platform

proposed for the collection and readout of the signal

at the array level combines the advantageous features

from two disparate readout paradigms into a single

unified monolithic readout framework.

An integrated digitization sub-system was also designed

and developed. The function of the digitization unit

is customized to the nature and profile of the detector

response generated at the output interface. The

unified system aims to present a complete blueprint

for integrated single-photon sensing and processing


This Event is For: Graduate • Faculty

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