M.S. Thesis Defense: Dhiraj Reddy Nallapa Yoge

Friday, April 13, 2018
11:30 a.m.
AVW 4185
Maria Hoo
301 405 3681
mch@umd.edu

ANNOUNCEMENT:  M.S. Thesis Defense

 

Name:  Dhiraj Reddy Nallapa Yoge

 

Committee: 

Professor Bruce Jacob

Professor Donald Yeung

Professor Rajeev Barua

 
Date/Time: Friday,  April 13th, 2018 at 11:30 am.

Location: AVW 4185

Title: Performance study of various modern DRAM architectures.


Several DRAM architectures exist with each differing in their performance, power and cost metrics. This thesis compares the performance and power characteristics of several such DRAM architectures which are compliant to JEDEC standard DDR protocols such as DDR3, DDR4, LPDDR3, LPDDR4, GDDR5 and HBM. To accurately model the differences in performance and power characteristics of these architectures, a new cycle level DRAM memory simulator has been designed and implemented from scratch. Several distinguishing features of these protocols such as - bankgroups in DDR4 and beyond, 32 activation window constraint in GDDR5, granularity of refresh at per rank level vs at per bank level and availability of low power modes such as self-refresh, dual command issue mode in HBM - are modelled and studied for their impact on workload performance and power consumption. The internal structure of DRAM exhibits different kinds of parallelisms such as channel level parallelism, rank level parallelism and bank level parallelism. The type and the degree of parallelism together with the associated DRAM command timing constraints determine the latency and bandwidth characteristics of any DRAM architecture. Abstract studies are performed to determine the potential of each of these parallelisms in attaining the maximum supported pin bandwidth for a set of SPEC 2006 CPU workloads. Finally, several real DRAM architecture designs belonging to each of the above mentioned protocols are studied to quantify their relative performance, power and cost trade off. 

 

Audience: Graduate  Faculty 

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