Course Information:

Lecture:	Tue Thu 2:00 - 3:15, EGR-1104
Mailing List:	enee759m-0101-spr00@coursemail.umd.edu
Required Text:	Hill, Jouppi, and Sohi (Eds), Readings in Computer Architecture, Morgan Kaufmann, 2000
Recommended Texts:	Weiss & Smith, POWER and PowerPC, Morgan Kaufmann, 1994 Shriver & Smith, The Anatomy of a High-Performance Microprocessor, IEEE Computer Society Press, 1998 Johnson, Superscalar Microprocessor Design, Prentice Hall, 1991

Instructor Information:

Professor:	Bruce L. Jacob, Assistant Professor, Electrical & Computer Engineering
Office:	1325 A.V. Williams Building
Phone:	(301) 405-0432
Email:
Office Hours:	Tuesday 3:15-4:30, Wednesday 1:00-3:00

Course Handouts and General Information:

• Syllabus.pdf
• PROJECT ZERO: Simple Superscalar Design
• Files for PROJECT ZERO (assembler, simulator, a few test files ...)
• Instruction Issue in the IBM 360/91 Integer Pipeline
• The ETCH trace-reading tools (see the README file)
• ***** MIDTERM TEST & SOLUTIONS *****
• final-prep-2000.pdf
• superspeculative.ps: A paper by Lipasti & Shen that significantly extends the limit of instruction-level parallelism through lots of speculation. This relates to the many discussions we've been having on data speculation.

Reading Assignments:

Week 1:	Overviews	Diefendorff 1999 (on-line) Smith & Sohi 1995 (on-line)
	For fun	Wharton 1994 & Paterson 1994 (on-line)
Week 2:	Overviews, cont'd	Rao & Fisher 1992 (p. 288)
Week 3:	Issues Then & Now	Anderson, Sparacio & Tomasulo 1967 (p. 185) Conte et al. 1995 (on-line) Smith & Pleszkun 1988 (p. 202)
Week 4:	Dynamic Scheduling	Smith 1989 (handout) Tomasulo 1967 (handout) Sohi & Vajapeyam 1987 (p. 244)
	For example	Yeager 1996 (p. 275) ... this is an extremely in-depth description of the MIPS R10000, including its implementation of a reorder buffer structure, support for precise interrupts, register renaming, etc.
Week 5:	Advanced Caches	Kroft 1981 (p. 380) Jouppi 1990 (p. 395) Wang, Baer & Levy 1989 (p. 434) Wheeler & Bershad 1992 (on-line)
	For example	Jacob et al. 1996 (on-line) ... this is an example of analytical cache modeling, as we talked about in class; a mathematical model is proposed that predicts observed behavior; the model is validated against simulated results; and the implications of the model are explored.
Week 6:	DRAM Architectures	Dipert 2000 (on-line) Cuppu et al. 1999 (on-line) Cuppu & Jacob 1999 (on-line)
Week 7:	Review & Midterm
Week 8:	Spring Break
Week 9:	Branch Prediction, Data Prediction	Smith 1981 (p. 214) Yeh & Patt 1991 (p. 228) Lee, Chen & Mudge 1997 (on-line) Sazeides & Smith 1997 (on-line) Lipasti, Wilkerson & Shen 1996 (on-line)
	For fun	Johnson 2000 (on-line) ... this is an intuitive description of metastability, which is very important when designing things like external interfaces, including interrupt lines; for example, you do not want external devices to set an internal latch--such as the interrupt bit in the processor state register--directly.
Week 10:	Low Power	Horowitz et al. 1994 (on-line) Gonzalez & Horowitz 1996 (on-line) The Transmeta white papers (on-line) Scott et al. 1998 (on-line) Fromm et al. 1997 (on-line)
	For example	Ebcioglu & Altman 1996 (on-line) ... DAISY is an example of using a VLIW core and dynamically translating instructions for a completely different ISA, to the point where you can fool the operating system -- much like the Transmeta Crusoe processor.
Week 11:	Memory Management	Jacob 1998a (on-line) Jacob 1998b (on-line) Kilburn et al. 1962 (p. 405) Clark & Emer 1985 (p. 418) Jacob 1998c (on-line)
Week 12:	HW/OS Interaction	Anderson, et al. 1991 (on-line) Liedtke 1993 (on-line) Liedtke 1995 (on-line) Ousterhout 1989 (on-line)
Wks 13/14:	New Ideas, Old Ideas	B. Smith 1981 (p. 342) Tullsen et al. 1996 (p. 350) Gokhale et al. 1995 (p. 542) Papworth 1996 (p. 660) Slater 1996 (p. 668) Yu 1996 (p. 681) MPR 1996 (on-line)

Additional Papers:

anderson1991:	"The interaction of architecture and operating system design." T. E. Anderson, H. M. Levy, B. N. Bershad, and E. D. Lazowska. In Proc. Fourth Int'l Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS-4), pp. 108-120, 1991. (click here for a postscript copy ... the PDF copy is viewable but prints out poorly)
conte1995:	"Optimization of instruction fetch mechanisms for high issue rates." T. M. Conte, K. N. Menezes, P. M. Mills, and B. A. Patel. In Proc. 22nd Annual International Symposium on Computer Architecture (ISCA'95), pp. 333-344, Santa Margherita Ligure, Italy, June 1995. (click here for a postscript copy ... the PDF copy is viewable but prints out poorly)
cuppu1999:	"A performance comparison of contemporary DRAM architectures." Vinodh Cuppu, Bruce Jacob, Brian Davis, and Trevor Mudge. In Proc. 26th International Symposium on Computer Architecture (ISCA'99), pp. 222-233. Atlanta GA, May 1999.
cuppu+jacob1999:	"Organizational design trade-offs at the DRAM, memory bus, and memory controller level: Initial results." Vinodh Cuppu and Bruce Jacob. University of Maryland Systems & Computer Architecture Group Technical Report UMD-SCA-1999-2. November 1999.
diefendorff1999:	"PC processor microarchitecture." Keith Diefendorff. Microprocessor Report, vol. 13, no. 9, pp. 16-22, July 12 2000.
dipert2000:	"The slammin, jammin, DRAM scramble." Brian Dipert. EDN, pp. 68-82, January 2000.
ebcioglu+altman1996:	"DAISY: Dynamic compilation for 100% architectural compatibility." Kemal Ebcioglu dn Erik Altman. IBM Research Report, September 1996. (click here for a postscript copy ... the PDF copy is viewable but prints out poorly)
fromm1997:	"The energy efficieny of IRAM structures." R. Fromm, S. Perissakis, N. Cardwell, C. Kozyrakis, B. McGaughy, D. Patterson, T. Anderson, and K. Yelick. In Proc. 24th Annual International Symposium on Computer Architecture (ISCA'97), pp. 327-337, June 1997.
gonzalez+horowitz1996:	"Energy dissipation in general purpose microprocessors." Ricardo Gonzalez and Mark Horowitz. IEEE Journal of Solid-State Circuits, 31(9), pp. 1277-1284, September 1996.
horowitz1994:	"Low-power digital design." M. Horowitz, T. Indermaur, and R. Gonzalez. In Proc. Symposium on Low Power Electronics, pp. 8-11, October 1994.
jacob1996:	"An analytical model for designing memory hierarchies." Bruce Jacob, Peter Chen, Seth Silverman, and Trevor Mudge. IEEE Transactions on Computers, vol. 45, no. 10, pp. 1180-1194. October 1996. (click here for a postscript copy ... the PDF copy is viewable but prints out poorly)
jacob1998a:	"Virtual memory: Issues of implementation." Bruce Jacob and Trevor Mudge. IEEE Computer, vol. 31, no. 6, pp. 33-43. June 1998.
jacob1998b:	"Virtual memory in contemporary microprocessors." Bruce Jacob and Trevor Mudge. IEEE Micro, vol. 18, no. 4, pp. 60-75. July/August 1998.
jacob1998c:	"A look at several memory management units, TLB-refill mechanisms, and page table organizations." Bruce Jacob and Trevor Mudge. In Proc. Eighth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'98), pp. 295-306. San Jose CA, October 1998.
johnson2000:	"Metastable persons." Howard Johnson. EDN, p. 30, March 16 2000.
lee+chen+mudge1997:	"The bi-mode branch predictor." Chih-Chieh Lee, I-Chen Chen, and Trevor Mudge. In Proc. 30th Annual International Symposium on Microarchitecture (MICRO-30), pp. 4-13. Research Triangle Park NC, December 1997. (click here for a postscript copy ... the PDF copy is viewable but prints out poorly)
liedtke1993:	"Improving IPC by kernel design." Jochen Liedtke. In Proc. Fourteenth ACM Symposium on Operating Systems Principles (SOSP-14). pages 175-187, 1993. (click here for a postscript copy ... the PDF copy is viewable but prints out poorly)
liedtke1995:	"On micro-kernel construction." Jochen Liedtke. In Proc. Fifteenth ACM Symposium on Operating Systems Principles (SOSP-15). 1995. (click here for a postscript copy ... the PDF copy is viewable but prints out poorly)
lipasti1996:	"Value locality and load value prediction." M. H. Lipasti, C. B. Wilkerson, and J. P. Shen. In Proc. Seventh Int'l Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS-7). Cambridge MA, October 1996. (click here for a postscript copy ... the PDF copy is viewable but prints out poorly)
mpr1996:	"Architects look to processors of future." Gordon Bell, Richard Sites, William Dally, David Ditzel, and Yale Patt. Microprocessor Report, vol. 10, no. 10, pp. 18-24, August 1996.
ousterhout1989:	"Why aren't operating systems getting faster as fast as hardware?." John Ousterhout. Technical Report WRL-TN-11, DEC Western Research Laboratory. October 1989. (click here for a postscript copy ... the PDF copy is viewable but prints out poorly)
sazeides+smith1997:	"The predictability of data values." Yiannakis Sazeides and Jim Smith. In Proc. 30th Annual International Symposium on Microarchitecture (MICRO-30). Research Triangle Park NC, December 1997. (click here for a postscript copy ... the PDF copy is viewable but prints out poorly)
scott1998:	"Designing the low-power M-CORE architecture." Jeff Scott, Lea Hwang Lee, John Arends, and Bill Moyer. In Proc. IEEE Power Driven Microarchitecture Workshop, pp. 145-150. Barcelona Spain, June 1998.
smith+sohi1995:	"The microarchitecture of superscalar processors." Jim Smith and Guri Sohi. Proceedings of the IEEE, December 1995.
transmeta2000a:	"The technology behind Crusoe processors." Alexander Klaiber. Transmeta Corporation white paper, January 2000.
transmeta2000b:	"Mobile platform benchmarks." Daniel McKenna. Transmeta Corporation white paper, January 2000.
transmeta2000c:	"Crusoe processor benchmark report." Transmeta Corporation white paper, January 2000.
wharton1994: paterson1994:	"Gary Kildall, industry pioneer, dead at 52." John Wharton. Microprocessor Report, vol. 8, no. 10, August 1994. "The origins of DOS: DOS creator gives his view of relationship between CP/M, MS-DOS." Letter to the editor from Tim Paterson. Published in Microprocessor Report, vol. 8, no. 13, October 1994.
wheeler+bershad1992:	"Consistency management for virtually indexed caches." In Proc. Fifth Int'l Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS-5), pp. 124-136. Boston MA, October 1992. (click here for a postscript copy ... the PDF copy is viewable but prints out poorly)