Supplementary information on the projects:

Motivation: There are numerous papers that talks about the "memory wall", and how difficult it is to continue to scale in performance due to the Von Neumann architecture of the separation of logic and memory. Your goal would be to come up with some interesting tidbits that helps to attack this bottleneck. Your project should provide something that is "better" in some way: lower latency, higher theoretical bandwidth, less expensive, less power consumption, or . . . . Then, when you present your project, you should make clear what it is that you've made "better".

Alternative memory system designs: There are two different alternative memory systems suggested in presentation slides. One design is the multi-drop bus with wave pipelined characteristic. The other suggested alternative design is one based on serial link topology. Upon completion of the project, the groups will be expected to minimally produce diagrams that illustrate chip architecture (similar to diagrams presented in class for SDRAM/DRDRAM), access protocol, command sets, command encoding, signaling technology, and simulation results that show the performance impact, positive or negative. Comparison to existing (DDR) SDRAM or DRDRAM systems would be very informative. Since each group will be asked to design a complete memory system, there are lots of work to be done. Architectural simulations, circuit level simulations. At least one person should be appointed to search ISSCC or Hot Interconnects conference proceedings for high speed I/O presentation, and use them as references for simulation or basis of design assumption. system level circuit simulation results to support the I/O data rate assumptions would also be impressive. There is now a starting reference point for the Wave pipelined memory on the class web page. The "serial link memory" starting point should be from Poulton's 1999 ISSCC signaling tutorial.

Address mapping/Memory request ordering: There are several papers by Sally McKee (now at the University of Utah) and Doug Burger. We have an existing simulation environment based on Simplescalar and simulates SDRAM/DRDRAM memory systems. Opportunities exist in tweaking the latency/bandwidth assumptions of the memory system. Your goal here would be to find a combination of address mapping algorithm and memory request ordering scheme that show a speedup, backedup by simulation results.

Page based commands: A good starting point is to look at Fred Chong's active memory web pages, and perhaps Berkeley's IRAM project. The idea here is to merge DRAM with logic, with perhaps minimal increases in logic, but will enable the memory chips to perform some taks with enormous speedup. The best designs would take existing memory systems, i.e. SDRAM, DRDRAM or DDR SDRAM, then integrate the addition to it. Incorporate the design, and simulate the speedup, perhaps with Boch.

Verilog memory controller design: The basic idea here is to take an existing RISC CPU core, and design a memory controller in verilog (behavioral or structural model) that interfaces to DRAM chips. The verilog model of the RISC CPU may be obtained fro Dr Jacob, and the verilog model of the DRAM chips themselves may be obtained from one of many memory manufacturers. For example, Micron has models that you may download from online.