|Lecture:||Tue Thu 2:00 - 3:15, ATL-2428|
|Required Text:||Jacob, Ng, & Wang, Memory Systems: Cache, DRAM, Disk, Morgan Kaufmann, 2008|
|Recommended Text:||Hennessy & Patterson, Computer Architecture: A Quantitative Approach, 4th Ed., Morgan Kaufmann|
|Recommended Text:||Smith & Franzon, Verilog Styles for Synthesis of Digital Systems, Prentice Hall|
|Professor:||Bruce L. Jacob, Electrical & Computer Engineering|
|Office:||1333 A.V. Williams Building|
|Office Hours:||Tue/Wed/Thu, Open-door policy ...|
|Teaching Assistant:||Eli Lorenzi|
|Office Hours:||to be determined|
Course Handouts and General Information:
Background on branch prediction:
This describes, among other things, the use of adaptive/dynamic state machines (e.g. saturating counters) to track branch behavior and to predict future behavior based on that observed past behavior.
A nice description of the branch-target buffer and a description of what Yeh & Patt call a "static training" branch prediction scheme in which a branch history (string of bits signifying taken/not-taken status of most recent branch outcomes) is used to generate a prediction. That prediction can be generated by profiling a set of benchmarks. The article also explores a few other adaptive state machines besides saturating counters.
By the way, the article is huge, weighing in at 16MB. Here is a 3MB file, with a bit of a image-quality tradeoff (I photocopied it from the original).
Combines the concept of the history-indexed table, as described in Lee & Smith  (called static training by Yeh & Patt) and the use of adaptive state machines, as described in Smith . Instead of putting a static prediction bit into the table, an adaptive state machine is put into each entry in the table. Note that later papers by Yeh & Patt change the name of the scheme to "two-level adaptive branch prediction" (dropping the "training").
Articles well worth reading:
|Project 1||29 Aug 2017||5 Sep 2017||p1.pdf||Project 1|
|Project 2||5 Sep 2017||3 Oct 2017||p2.pdf||Project 2|
|Project 3||5 Oct 2017||9 Nov 2017||p3.pdf||Project 3|
Documents describing the RiSC-16:
|File Name||Document Name||Document Description|
|F2014-RiSC-ISA.pdf||The RiSC-16 Instruction-Set Architecture||Describes the instruction-set architecture: machine-code forms, assembly-code forms, etc.|
|F2002-RiSC-seq.pdf||RiSC-16: Sequential Implementation||Describes a sequential implementation of the architecture: control flow, data flow, etc.|
|F2002-RiSC-pipe.pdf||The Pipelined RiSC-16||Describes a pipelined implementation of the architecture: control flow, data flow, pipeline stages, pipeline hazards, data forwarding, etc.|