Course Information:

Lecture:	Tue Thu 2:00 - 3:15, CHE-2108
Mailing List:	enee646-0101-fall02@coursemail.umd.edu
Required Text:	Hennessy & Patterson, Computer Architecture: A quantitative Approach, 3rd Ed., Morgan Kaufmann, 2002
Recommended Text:	Bhasker, A Verilog HDL Primer, Star Galaxy Publishing

Instructor Information:

Professor:	Bruce L. Jacob, Assistant Professor, Electrical & Computer Engineering
Office:	1325 A.V. Williams Building
Phone:	(301) 405-0432
Email:	blj@eng.umd.edu
Office Hours:	To be decided on the first day of class ...

TA:	Himabindu Kakaraparthi
Email:	hima@eng.umd.edu
Mailbox:
Office Hours:	TuTh 10-11:00, EGR 1153
Recitations:	Sec1: Sec2:

Course Handouts and General Information:

• Syllabus.pdf
• verilog-handbook.pdf. This is a concise overview of the Verilog programming language.
• realize-verilog.pdf. Gives a functional view of Verilog; i.e. if you want to build a processor model, this shows how. However, it confuses blocking/non-blocking assignments (calls "=" non-blocking and "<=" blocking). Otherwise, it is a decent overview.
• IBM 360/91's Out-of-Order Fixed-Point Pipe. Describes (my guess as to) the implementation of instruction enqueue, issue, and commit in the IBM 360/91 fixed-point pipeline. In contrast, the 360/91's floating-point pipeline is famous for its implementation of Tomasulo's algorithm, which is well documented.
• "PC processor microarchitecture." Keith Diefendorff. Microprocessor Report, vol. 13, no. 9, pp. 16-22, July 12 2000.
• A Crash Course in C Programming

Articles well worth reading:

• MIPS-R10000.pdf
• DynamicScheduling.pdf
• Tomasulo.pdf
• ReorderBuffer.pdf

Assignments:

ID	Out	Due	Write-up	Distribution	Updated
Project 1	3 Sep 2002	24 Sep 2002	p1.pdf	Project 1	5 Sep 2002
Project 2	26 Sep 2002	21 Oct 2002	p2.pdf	Project 2	5 Sep 2002
Project 3	24 Oct 2002	19 nov 2002	p3.pdf	Project 3	24 Oct 2002

Documents describing the RiSC-16:

File Name	Document Name	Document Description
F2002-RiSC-ISA.pdf	The RiSC-16 Instruction-Set Architecture	Describes the instruction-set architecture: machine-code forms, assembly-code forms, etc.
F2002-RiSC-seq.pdf	RiSC-16: Sequential Implementation	Describes a sequential implementation of the architecture: control flow, data flow, etc.
F2002-RiSC-pipe.pdf	The Pipelined RiSC-16	Describes a pipelined implementation of the architecture: control flow, data flow, pipeline stages, pipeline hazards, data forwarding, etc.

Source Code:

File Name	Description of Contents
a2	A rudimentary RiSC-16 assembler (SPARC executable binary file).
a2.c	C code for the rudimentary RiSC-16 assembler above.