//
// synthesis examples
//

`define ADD	3'd0
`define ADDI	3'd1
`define NAND	3'd2
`define LUI	3'd3
`define SW	3'd4
`define LW	3'd5
`define BNE	3'd6
`define JALR	3'd7
`define EXTEND	3'd7

module alu1 (op, alu1, alu2, bus);
	input	[2:0]	op;
	input	[15:0]	alu1;
	input	[15:0]	alu2;
	output	[15:0]	bus;

	assign bus =	(op == `ADD) ? alu1 + alu2 :
			(op == `NAND) ? ~(alu1 & alu2) :
			alu2;

endmodule


module alu2 (op, alu1, alu2, bus);
	input	[2:0]	op;
	input	[15:0]	alu1;
	input	[15:0]	alu2;
	output	[15:0]	bus;

	assign bus =	(op == `ADD) ? alu1 + alu2 :
			~(alu1 & alu2) ;

endmodule


module alu3 (op, alu1, alu2, bus);
	input	[2:0]	op;
	input	[15:0]	alu1;
	input	[15:0]	alu2;
	output	[15:0]	bus;
	reg	[15:0]	bus;

	always @ (op or alu1 or alu2) begin
		if (op == `ADD) bus = alu1 + alu2;
		if (op == `NAND) bus = ~(alu1 & alu2);
	end

endmodule


module alu4 (op, alu1, alu2, bus);
	input	[2:0]	op;
	input	[15:0]	alu1;
	input	[15:0]	alu2;
	output	[15:0]	bus;
	reg	[15:0]	bus;

	always @ (op or alu1 or alu2) begin
		if (op == `ADD) bus = alu1 + alu2;
		else if (op == `NAND) bus = ~(alu1 & alu2);
		else bus = alu2;
	end

endmodule


module alu5 (op, alu1, alu2, bus);
	input	[2:0]	op;
	input	[15:0]	alu1;
	input	[15:0]	alu2;
	output	[15:0]	bus;
	reg	[15:0]	bus;

	always @ (op or alu1 or alu2) 
	case (op)
		`ADD:	bus = alu1 + alu2;
		`NAND:	bus = ~(alu1 & alu2);
	endcase

endmodule


module alu6 (op, alu1, alu2, bus);
	input	[2:0]	op;
	input	[15:0]	alu1;
	input	[15:0]	alu2;
	output	[15:0]	bus;
	reg	[15:0]	bus;

	always @ (op or alu1 or alu2)
	case (op)
		`ADD:		bus = alu1 + alu2;
		`NAND:		bus = ~(alu1 & alu2);
		default:	bus = alu2;
	endcase

endmodule


module alu7 (op, alu1, alu2, bus);
	input	[2:0]	op;
	input	[15:0]	alu1;
	input	[15:0]	alu2;
	output	[15:0]	bus;
	reg	[15:0]	bus;

	always @ (op or alu1 or alu2) begin
		if (op == `ADD) bus <= alu1 + alu2;
		else if (op == `NAND) bus <= ~(alu1 & alu2);
		else bus <= alu2;
	end

endmodule


module alu8 (op, alu1, alu2, bus);
	input	[2:0]	op;
	input	[15:0]	alu1;
	input	[15:0]	alu2;
	output	[15:0]	bus;
	reg	[15:0]	bus;

	always @ (op or alu1 or alu2) 
	case (op)
		`ADD:	bus <= alu1 + alu2;
		`NAND:	bus <= ~(alu1 & alu2);
	endcase

endmodule


module alu9 (op, alu1, alu2, bus);
	input	[2:0]	op;
	input	[15:0]	alu1;
	input	[15:0]	alu2;
	output	[15:0]	bus;
	reg	[15:0]	bus;

	always @ (op or alu1 or alu2)
	case (op)
		`ADD:		bus <= alu1 + alu2;
		`NAND:		bus <= ~(alu1 & alu2);
		default:	bus <= alu2;
	endcase

endmodule