Course Information:

Lecture:	TuTh 2:00 - 3:15, EGR-0135
Mailing List:	enee446-0101-spr06@coursemail.umd.edu
Required Text:	Smith & Franzon, Verilog Styles for Synthesis of Digital Systems, Prentice Hall 2000
Recommended Text:	Hennessy & Patterson, Computer Architecture: A quantitative Approach, 2nd Ed., Morgan Kaufmann, 1996

Instructor Information:

Professor:	Bruce L. Jacob, Electrical & Computer Engineering
Office:	1325 A.V. Williams Building
Phone:	(301) 405-0432
Email:
Office Hours:	Open-door, for now ...

Course Handouts and General Information:

• Syllabus.pdf
• verilog-handbook.pdf. This is a concise overview of the Verilog programming language.
• realize-verilog.pdf. Gives a functional view of Verilog; i.e. if you want to build a processor model, this shows how. However, it confuses blocking/non-blocking assignments (calls "=" non-blocking and "<=" blocking). Otherwise, it is a decent overview.
• IBM 360/91's Out-of-Order Fixed-Point Pipe. Describes (my guess as to) the implementation of instruction enqueue, issue, and commit in the IBM 360/91 fixed-point pipeline. In contrast, the 360/91's floating-point pipeline is famous for its implementation of Tomasulo's algorithm, which is well documented.
• "PC processor microarchitecture." Keith Diefendorff. Microprocessor Report, vol. 13, no. 9, pp. 16-22, July 12 1999.

Assignments:

ID	Out	Due	Write-up	Distribution	Updated
Project 1	26 Jan 2006	07 Feb 2006	p1.pdf	Project 1	26 Jan 2006
Project 2	16 Feb 2006	14 Mar 2006	p2.pdf	Project 2	23 Feb 2006
Synthesis 1	23 Feb 2006	02 Mar 2006	s1.pdf	s1examples.v	23 Feb 2006
Project 3	04 Apr 2006	09 May 2006	p3.pdf	Project 3	14 Apr 2006

Documents describing the RiSC-16:

File Name	Document Name	Document Description
RiSC-isa.pdf	The RiSC-16 Instruction-Set Architecture	Describes the instruction-set architecture: machine-code forms, assembly-code forms, etc.
RiSC-seq.pdf	RiSC-16: Sequential Implementation	Describes a sequential implementation of the architecture: control flow, data flow, etc.

Source Code:

File Name	Description of Contents
a.c	C code for a rudimentary RiSC-16 assembler.
laplace.s	RiSC-16 assembly code for a decent-sized benchmark, written by Vince Weaver and Asher Lazarus -- former enee350 and enee759m students.