ENEE446 (Section 0101) Digital Computer Design by P. Petrov

Spring 2005

Class Information

Instructor: Peter Petrov, AVW 1421, ppetrov at ece dot umd dot edu
Office hours: TuTh 11:00am - 12:00pm
Class hours: TuTh 2:00pm - 3:15pm, EGR 0135
Required text: Computer Architecture: A Quantitative Approach, 3th Ed., by Hennessy and Patterson.
Course Syllabus
Project information

During the course of this class we will develop a simple processor by using the Verilog hardware description language (HDL). Three project assignments will be given out each of them adding a level of sophistication to the processor architecture. The projects will implement the RiSC-16 architecture, which is a teaching architecture adapted by Bruce Jacob (University of Maryland) from the Little Computer (LC-896) developed by Peter Chen at the University of Michigan. The following pdf documents contain detailed information regarding the RiSC-16 architecture.
RiSC-isa.pdf - RiSC-16 Instruction Set Architecture Manual.
RiSC-seq.pdf - RiSC-16 Sequential Implementation Manual.
RiSC-pipe.pdf - RiSC-16 Pipelined Implementation Manual.
RiSC.c - RiSC-16 functional simulator implemented in C. This is useful for verification of your designs.
a.c - RiSC-16 assembler. Use this to compile RiSC-16 assembly programs to binaries.
laplace.s - Assembly code for a decent-sized benchmark, written by Vince Weaver and Asher Lazarus -- former enee350 and enee759m students.

Virtua Memory: Issues of Implementation - Very useful reading for virtual memory implementations

The following two pdf documents contain very useful and brief descriptions of the Verilog language.
Verilog Handbook - A brief overview of Verilog.
Verilog Computation Model - Gives a functional overview of how to model various harwdare structures with Verilog. It confuses, however, blocking/non-blocking assignments (calls "=" non-blocking and "<= blocking). Other than that, it is a very usefull overview.

In order to run the Verilog simulator, you have to log in with your glue account on the departmental solaris workstations. After you log in, your have to execute the cadance shell, by running the following command:
You will see a number of options for using different cadence packages. Please select ldv (Logic Design and Verification) by typing ldv. After that you will have a shell from which you can execute the verilog simulator. You can either use the command "verilog" to run the Verilog-XL simulator, or the command "ncverilog" to run an alternative Verilog simulator, which takes a bit longer to start the simulation, but then it is faster. From within the Cadence shell, you can execute your favorite Unix shell (for example, tcsh), and then still be able to run the Verilog simulators from within the standard Unix shell.

Project assignments:
Project 1. Assigned on Feb 8. Due Feb 22, 8pm. Project 1 files.
The due date for Project 1 has been extended to Saturday, 26 Feb, 11:59pm

Homework 1. The following problems from the textbook:
1.2, 1.3, 1.4, 1.7, 1.16, 2.1, 2.2, 2.3, 2.4, 2.6, 2.11, 2.12, 2.15, 2.19, A.1, A.2, A.3, A.4, A.5, A.6, A.7, A.13
Solutions for Homework-1 problems have been posted to umd.blackboard.com.

Project 2. Assigned on Feb 24. Due March 19 (Saturday), 11:59pm. Project 2 files.
For Project 2 you can work in groups of two, if you want to. Please, send me an email by March 15 stating who your partner is, if your decide to work in a group of two, or indicate that you are working by yourself.

Midterm-1 will be in class on March 8, Tuesday.

Homework 2. The following problems from the textbook:
A.13, 3.2, 3.3, 3.7, 3.8, 3.9, 3.14, 3.18, 3.21, 3.22, 4.2, 4.3, 4.7, 4.8a, 4.9, 4.16, 4.17, 4.23, 4.25

Midterm-2 will be in class on April 12, Tuesday.

Project 3. Assigned on April 8. Due May 13 (Friday), 11:59pm. Project 3 files.
For Project 3 you can work in groups of two, if you want to. Please, send me an email by April 17 stating who your partner is, if your decide to work in a group of two, or indicate that you are working by yourself.

The Porject 3 deadline has been extended to May 15 (Sunday), 11:59pm. This is a firm deadline and projects submitted after that will not be graded.

Homework 3. The following problems from the textbook:
5.6, 5.7, 5.12, 5.16, 5.17, 5.18, 5.19, 6.4, 6.9, 6.10