module tb_fibonacci(); `define clock_cycle 10 // Inputs to fibonacci calcutor reg [4:0] input_number; reg reset_n; reg go; reg clk; // outputs from fibonacci calculator wire done; wire [15:0] output_number; // testbench variable reg error; reg calculation_one; reg calculation_two; reg calculation_three; reg [11:0] cycles; reg [11:0] cycles1; reg [11:0] cycles2; reg [11:0] cycles3; // Instantiate the fibonacci FSM fibonacci uut ( .input_number(input_number), .reset_n(reset_n), .go(go), .clk(clk), .done(done), .output_number(output_number) ); // clock generation initial begin clk = 0; forever #(`clock_cycle/2) clk = ~clk; end initial begin reset_n = 0; #(`clock_cycle); reset_n = 1; end initial begin //Initialization go = 1'b0; input_number = 5'd0; error = 1'b0; cycles = 12'd0; cycles1 = 12'd0; cycles2 = 12'd0; cycles3 = 12'd0; calculation_one = 1'b0; calculation_two = 1'b0; calculation_three = 1'b0; #(2*(`clock_cycle)); //First test number @ (negedge clk); input_number = 22; go = 1; wait (done ==1); $strobe("Fibonacci of 22 = %d\n", output_number); #1; if(output_number == 28657) //Error check output $strobe("This is correct.\n"); else begin $strobe("This is incorrect.\n"); error = 1'b1; end go = 0; wait (done ==0); #(`clock_cycle); reset_n = 0; #(`clock_cycle); reset_n = 1; #(`clock_cycle); //Second test number @ (negedge clk); input_number = 10; go = 1; wait (done ==1); $strobe("Fibonacci of 10 = %d\n", output_number); #1; if(output_number == 89) $strobe("This is correct.\n"); else begin $strobe("This is incorrect.\n"); error = 1'b1; end go = 0; wait (done ==0); #(`clock_cycle); reset_n = 0; #(`clock_cycle); reset_n = 1; #(`clock_cycle); //Third test number @ (negedge clk); input_number = 20; go = 1; wait (done ==1); $strobe("Fibonacci of 20 = %d\n", output_number); #1; if(output_number == 10946) $strobe("This is correct.\n"); else begin $strobe("This is incorrect.\n"); error = 1'b1; end go = 0; #(`clock_cycle); //Any errors found? if(error == 1'b0) $display("There were no errors.\n"); else $display("There was at least one error.\n"); #(`clock_cycle); $display("%0d", cycles1, " cycles to first calculation.\n"); $display("%0d", cycles2, " cycles for second calculation.\n"); $display("%0d", cycles3, " cycles for third calculation.\n"); $display("%0d", cycles, " cycles for all three calculations .\n"); $stop; end initial begin calculation_one = 1'b0; calculation_two = 1'b0; calculation_three = 1'b0; wait (go == 1); calculation_one = 1'b1; wait (done == 1); calculation_one = 1'b0; wait (done == 0); wait (go == 1); calculation_two = 1'b1; wait (done == 1); calculation_two = 1'b0; wait (done == 0); wait (go == 1); calculation_three = 1'b1; wait (done == 1); calculation_three = 1'b0; end always@(negedge clk) begin if (calculation_one == 1'b1 || calculation_two == 1'b1 || calculation_three== 1'b1) cycles = cycles + 12'b1; if (calculation_one == 1'b1) cycles1 = cycles1 + 12'b1; if (calculation_two == 1'b1) cycles2 = cycles2 + 12'b1; if (calculation_three == 1'b1) cycles3 = cycles3 + 12'b1; end endmodule