Example 4 --------- Here is the previous example with a bunch of NOPs inserted so that there are no data hazards to worry about. Therefore, the values that the ALU uses should be those that came directly from the register file. Note that I added a label "loop" to point to the ADD instruction, since the "-2" value no longer has meaning (I've added a bucnh of NOP instructions, so the branch now points into the middle of a group of NOPs). lw 1 0 data1 $1= mem[data1] nop nop nop loop add 2 1 1 nop nop nop beq 1 2 loop nop nop nop halt nop nop nop data1 .fill 12345 This assembles to the following LC-897 machine-code: 4090 e000 e000 e000 04a0 e000 e000 e000 857b e000 e000 e000 c000 e000 e000 e000 3039 When executed, we get the following output. Note that we read the operands directly from the register file. To test your simulators, you might want to look at all of the old test cases for Project 1 and add a bunch of NOP instructions to get rid of data hazards. Then once you get simple pipelining to work you can add feedback to solve the hazard problems (and remove the NOPs). memory[0]=4090 memory[1]=e000 memory[2]=e000 memory[3]=e000 memory[4]=4a0 memory[5]=e000 memory[6]=e000 memory[7]=e000 memory[8]=857b memory[9]=e000 memory[10]=e000 memory[11]=e000 memory[12]=c000 memory[13]=e000 memory[14]=e000 memory[15]=e000 memory[16]=3039 17 memory words instruction memory: instrMem[ 0 ] = lw 1 0 16 instrMem[ 1 ] = nop instrMem[ 2 ] = nop instrMem[ 3 ] = nop instrMem[ 4 ] = add 2 1 1 instrMem[ 5 ] = nop instrMem[ 6 ] = nop instrMem[ 7 ] = nop instrMem[ 8 ] = beq 2 1 -5 instrMem[ 9 ] = nop instrMem[ 10 ] = nop instrMem[ 11 ] = nop instrMem[ 12 ] = halt instrMem[ 13 ] = nop instrMem[ 14 ] = nop instrMem[ 15 ] = nop instrMem[ 16 ] = nand 3 4 0 @@@ state before cycle 0 starts pc 0 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 0 reg[ 2 ] 0 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction nop pcPlus1 0 IDEX: instruction nop pcPlus1 0 readRegA 0 readRegB 0 offset 0 EXMEM: instruction nop branchTarget 0 aluResult 0 readRegB 0 MEMWB: instruction nop writeData 0 WBEND: instruction nop writeData 0 @@@ state before cycle 1 starts pc 1 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 0 reg[ 2 ] 0 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction lw 1 0 16 pcPlus1 1 IDEX: instruction nop pcPlus1 0 readRegA 0 readRegB 0 offset 0 EXMEM: instruction nop branchTarget 0 aluResult 0 readRegB 0 MEMWB: instruction nop writeData 0 WBEND: instruction nop writeData 0 @@@ state before cycle 2 starts pc 2 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 0 reg[ 2 ] 0 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction nop pcPlus1 2 IDEX: instruction lw 1 0 16 pcPlus1 1 readRegA 0 readRegB 0 offset 16 EXMEM: instruction nop branchTarget 0 aluResult 0 readRegB 0 MEMWB: instruction nop writeData 0 WBEND: instruction nop writeData 0 @@@ state before cycle 3 starts pc 3 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 0 reg[ 2 ] 0 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction nop pcPlus1 3 IDEX: instruction nop pcPlus1 2 readRegA 0 readRegB 0 offset 0 EXMEM: instruction lw 1 0 16 branchTarget 17 aluResult 16 readRegB 0 MEMWB: instruction nop writeData 0 WBEND: instruction nop writeData 0 @@@ state before cycle 4 starts pc 4 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 0 reg[ 2 ] 0 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction nop pcPlus1 4 IDEX: instruction nop pcPlus1 3 readRegA 0 readRegB 0 offset 0 EXMEM: instruction nop branchTarget 2 aluResult 0 readRegB 0 MEMWB: instruction lw 1 0 16 writeData 12345 WBEND: instruction nop writeData 0 @@@ state before cycle 5 starts pc 5 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 12345 reg[ 2 ] 0 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction add 2 1 1 pcPlus1 5 IDEX: instruction nop pcPlus1 4 readRegA 0 readRegB 0 offset 0 EXMEM: instruction nop branchTarget 3 aluResult 0 readRegB 0 MEMWB: instruction nop writeData 0 WBEND: instruction lw 1 0 16 writeData 12345 @@@ state before cycle 6 starts pc 6 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 12345 reg[ 2 ] 0 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction nop pcPlus1 6 IDEX: instruction add 2 1 1 pcPlus1 5 readRegA 12345 readRegB 12345 offset 32 EXMEM: instruction nop branchTarget 4 aluResult 0 readRegB 0 MEMWB: instruction nop writeData 0 WBEND: instruction nop writeData 0 @@@ state before cycle 7 starts pc 7 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 12345 reg[ 2 ] 0 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction nop pcPlus1 7 IDEX: instruction nop pcPlus1 6 readRegA 0 readRegB 0 offset 0 EXMEM: instruction add 2 1 1 branchTarget 37 aluResult 24690 readRegB 12345 MEMWB: instruction nop writeData 0 WBEND: instruction nop writeData 0 @@@ state before cycle 8 starts pc 8 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 12345 reg[ 2 ] 0 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction nop pcPlus1 8 IDEX: instruction nop pcPlus1 7 readRegA 0 readRegB 0 offset 0 EXMEM: instruction nop branchTarget 6 aluResult 0 readRegB 0 MEMWB: instruction add 2 1 1 writeData 24690 WBEND: instruction nop writeData 0 @@@ state before cycle 9 starts pc 4 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 12345 reg[ 2 ] 24690 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction beq 2 1 -5 pcPlus1 9 IDEX: instruction nop pcPlus1 8 readRegA 0 readRegB 0 offset 0 EXMEM: instruction nop branchTarget 7 aluResult 0 readRegB 0 MEMWB: instruction nop writeData 0 WBEND: instruction add 2 1 1 writeData 24690 @@@ state before cycle 10 starts pc 5 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 12345 reg[ 2 ] 24690 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction add 2 1 1 pcPlus1 5 IDEX: instruction beq 2 1 -5 pcPlus1 9 readRegA 12345 readRegB 24690 offset -5 EXMEM: instruction nop branchTarget 8 aluResult 0 readRegB 0 MEMWB: instruction nop writeData 0 WBEND: instruction nop writeData 0 @@@ state before cycle 11 starts pc 9 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 12345 reg[ 2 ] 24690 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction nop pcPlus1 0 IDEX: instruction nop pcPlus1 0 readRegA 0 readRegB 0 offset 0 EXMEM: instruction beq 2 1 -5 branchTarget 4 aluResult 0 readRegB 24690 MEMWB: instruction nop writeData 0 WBEND: instruction nop writeData 0 @@@ state before cycle 12 starts pc 10 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 12345 reg[ 2 ] 24690 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction nop pcPlus1 10 IDEX: instruction nop pcPlus1 0 readRegA 0 readRegB 0 offset 0 EXMEM: instruction nop branchTarget 0 aluResult 0 readRegB 0 MEMWB: instruction beq 2 1 -5 writeData 0 WBEND: instruction nop writeData 0 @@@ state before cycle 13 starts pc 11 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 12345 reg[ 2 ] 24690 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction nop pcPlus1 11 IDEX: instruction nop pcPlus1 10 readRegA 0 readRegB 0 offset 0 EXMEM: instruction nop branchTarget 0 aluResult 0 readRegB 0 MEMWB: instruction nop writeData 0 WBEND: instruction beq 2 1 -5 writeData 0 @@@ state before cycle 14 starts pc 12 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 12345 reg[ 2 ] 24690 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction nop pcPlus1 12 IDEX: instruction nop pcPlus1 11 readRegA 0 readRegB 0 offset 0 EXMEM: instruction nop branchTarget 10 aluResult 0 readRegB 0 MEMWB: instruction nop writeData 0 WBEND: instruction nop writeData 0 @@@ state before cycle 15 starts pc 13 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 12345 reg[ 2 ] 24690 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction halt pcPlus1 13 IDEX: instruction nop pcPlus1 12 readRegA 0 readRegB 0 offset 0 EXMEM: instruction nop branchTarget 11 aluResult 0 readRegB 0 MEMWB: instruction nop writeData 0 WBEND: instruction nop writeData 0 @@@ state before cycle 16 starts pc 14 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 12345 reg[ 2 ] 24690 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction nop pcPlus1 14 IDEX: instruction halt pcPlus1 13 readRegA 0 readRegB 0 offset 0 EXMEM: instruction nop branchTarget 12 aluResult 0 readRegB 0 MEMWB: instruction nop writeData 0 WBEND: instruction nop writeData 0 @@@ state before cycle 17 starts pc 15 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 12345 reg[ 2 ] 24690 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction nop pcPlus1 15 IDEX: instruction nop pcPlus1 14 readRegA 0 readRegB 0 offset 0 EXMEM: instruction halt branchTarget 13 aluResult 0 readRegB 0 MEMWB: instruction nop writeData 0 WBEND: instruction nop writeData 0 @@@ state before cycle 18 starts pc 16 data memory: dataMem[ 0 ] 16528 dataMem[ 1 ] -8192 dataMem[ 2 ] -8192 dataMem[ 3 ] -8192 dataMem[ 4 ] 1184 dataMem[ 5 ] -8192 dataMem[ 6 ] -8192 dataMem[ 7 ] -8192 dataMem[ 8 ] -31365 dataMem[ 9 ] -8192 dataMem[ 10 ] -8192 dataMem[ 11 ] -8192 dataMem[ 12 ] -16384 dataMem[ 13 ] -8192 dataMem[ 14 ] -8192 dataMem[ 15 ] -8192 dataMem[ 16 ] 12345 registers: reg[ 0 ] 0 reg[ 1 ] 12345 reg[ 2 ] 24690 reg[ 3 ] 0 reg[ 4 ] 0 reg[ 5 ] 0 reg[ 6 ] 0 reg[ 7 ] 0 IFID: instruction nop pcPlus1 16 IDEX: instruction nop pcPlus1 15 readRegA 0 readRegB 0 offset 0 EXMEM: instruction nop branchTarget 14 aluResult 0 readRegB 0 MEMWB: instruction halt writeData 0 WBEND: instruction nop writeData 0 machine halted total of 18 cycles executed