ENEE312H Spring 2006

 

Homework

1.      Diode: 3.2 and 3.4, due next Thursday (2/9/2006) Solution1

2.      DC bias for bipolar transistor: 5.76, 5.77, 5.78, due next Thursday (2/16/2006) Solution2

3.      DC bias for bipolar transistor: 5.79, 5.90, due next Thursday (2/23/2006) Solution3

4.      Small signal analysis of bipolar transistor amplifiers: Solution4

A. Be familiar with table 5.6 (by re-deriving the results and understand the physical meaning and circuit characteristics)

B. 5.104, 5.105, and 5.124.

C. Reproduce by yourself the pspice simulation shown in Fig. 5.82 (Output voltage as a function of frequency). The full circuit is shown in Fig. 5.81, as part of the example 5.21. Turn in your pspice schematic (circuit diagram) or text program, and plots showing the voltage gain, and, separately, the output phase, as a function of frequency. The frequency should cover the range of interest.

5.      Due March 28, Tuesday Solution5

[This part is for your reading assignment: (a) Derive the Miller theorem (page 578) by yourself --- details are in the textbook. (b) Read and get familiar with Appendix E. (c) Read/understand section 6.6.]

(a) Transfer function: T(s)=100s/[(1+s/106)(s+104)], s=jw, and w goes from 1(1/s) to 1010(1/s).

Inspect the transfer function and identify the AM, TL(s), and TH(s). Plot the Bode plots, including the amplitude vs. frequency and the phase vs. frequency, for (1) the midband gain; (2) the low frequency transfer function; and (3) the high frequency transfer function.

(b) 5.130 (a typical problem in analysis)

(c) 6.68 (CS high frequency performance)

(d) 6.70 (CE high frequency performance)

*Note: for 6.68 and 6.70, try do the complete analysis by yourself (do not refer to the existing formula in the textbook)

(e) 4.54 (MOS with an active load)

(f) 4.77 (typical MOS problem)

6. Due May 2, Tuesday Solution6

(a) 8.26 (identify feedback topology)

(b) 8.29 (series-shunt)

(c) 8.37 (series-series)

(d) 8.48 (shunt-shunt)

7. Due May 9, Tuesday Solution7

(a) 11.16 ring oscillator

(b) 11.17 ring oscillator

(c) 11.26, DRAM operation

 

Progress

Device physics link (handout and references)

Bode Plot handout

 

 

Semiconductor Devices and Analog Electronics; (3 credits) Prerequisite: ENEE 302 and completion of all lower-division technical courses in the EE curriculum. Restricted to students with a 09090 major code. See above note. The basic physical operation of P-N junction diodes, MOSFET's and bipolar transistors. Basic transistor circuit configurations (CE, CC, CB, CS, CD, CG). DC bias; small signal analysis. Simple multi-transistor circuits: diff-amplifier, current mirror. Frequency response.

 

 

Prof. Chia-Hung Yang (http://www.ece.umd.edu/~yang)

        Office: Room 1323, AVWII

        Office hours: Monday 4-5p.m., and Wednesday 4-5p.m.

        Phone: (301)405-3673; e-mail: yang@ece.umd.edu

 

        Textbook: Microelectronics circuits by Sedra and Smith, 4th edition

        TuTh: 3:30pm- 4:45pm (PLS 1117)

        Recitation hour: Tu: 8:00am- 8:50am (EGL 1202)

        Grading method: Homework, 10%; midterm, 40%; and final, 50% (A: 85%; B: 75%; C: 65%; D: 55%; F: < 55%)

        Midterm exam: Close-book, written exam., bring a calculator

        Final exam: Close-book, written exam., bring a calculator

        Teaching Assistant: Mr. Rakesh Panda, panda@umd.edu (Office: EGL Building Room 1153, Monday 11a.m.-12noon and Tuesday 4-5 p.m.)

        Academic calendar for SPRING TERM 2006

Classes Start 1/25/06 (Wednesday)

Spring Break 3/20/06 (Monday) through 3/24/06 (Friday)

Last Class 5/11/06 (Thursday)

Study Day 5/12/06 (Friday)

Final Exams Start 5/13/06 (Saturday)

Final Exams End 5/19/06 (Friday)

Senior Day 5/20/06 (Saturday)

Main Spring Commencement Ceremony 5/21/06 (Sunday Evening)

College Commencement Ceremonies 5/22/06 (Monday)

 

First assignment: Review chapter 3, 4, and 5. Understand the concept of equivalent circuits.

 

Useful links:

1. Silicon wafer processing http://www.processpecialties.com/siliconp.htm

2. Laplace transform: http://www.answers.com/main/ntquery?method=4&dsid=2222&dekey=Laplace+transform&gwp=8&curtab=2222_1

3. MOSFET fabrication: http://micro.magnet.fsu.edu/electromag/java/transistor

4. ECL logic family, an example: 4 input AND/NAND gate http://www.onsemi.com/PowerSolutions/product.do?id=MC100E104FNR2