ENEE 244: Digital Logic Design


Fall 2006

Selected Notes

Solution to Exam 1

TA Office Hours

Vishal Khandelwal:
    Section 0102: Wed 11:30-12:30pm AVW 2356

    Section 0103: Thurs 2-3pm AVW 2356
Rania Mameesh
    10:00-12:00 Mondays.
     Thursdays starting at 6:00 (kind of open ended)


Several of you have expressed confusion regarding the meaning of a minimal SOP form. Although this is a general concept, in this course we are interested in minimizing the total number of literals.

Example: f = x'y' + x'y Total Number of Literals = 4
                    = x' Total Number of Literals = 1

Annoucenment: First Midterm Oct 17th, In Class


Instructor: Dr Ankur Srivastava
                                1349 A.V. Williams Building
                              301 405 0434,

Textbooks: Digital Principles and Design, Donald Givone, McGraw Hill 2003

Lecture Information Time: Tuesday and Thursday 12:30pm to 1:45pm JMP 3201
Instructor: Dr Ankur Srivastava, 1349 A.V. Williams Building,,
Office Hours: Tuesday and Thursday 11:15am to 12:15am , or by appointment
Grading Policy Homework : 20 % 2 Midterms : 20% Each End Term: 40%



Broad Course Topics (subject to change)
1. Binary Numbers a. Binary Arithmetic b. Binary Conversion c. Binary Codes d. Error Detection and Correction
2. Boolean Algebra a. Canonical Forms b. Boolean Manipulations c. Gates and Combinational Networks d. Don t Cares e. Gate Properties
3. Simplification of Boolean Algebra, a. Prime Implicants b. Karnaugh Maps c. Quine-McCluskey Methods
4. Logic Devices and Components a. Adders, Subtractersb. Decoders, Encoders, Multiplexers c. PLAs and PALs, ROMs
5. Latches and Flip Flops
6. Sequential and Synchronous and Asynchronous Circuits
7. Wired Logic, Control Logic and Logic Gate Characteristics

TA: Vishal Khandelwal , Rania Mameesh  and Saeed Esmaili Sardari

Questions and Comments: