ENEE 244 (Sections 0201-0205) Digital Logic Design by P. Petrov
Homework Assignment 4. Due on Monday, Dec. 15, by 2:00pm in Navik's office - Kim Building, room 2243.
Homework Assignment 3. Due on Wednesday, Nov. 19, in class or instructor's office by 11:00am.
Homework Assignment 2. Due on Wednesday, Oct. 22, in class or instructor's office by 11:00am.
Homework Assignment 1. Due on Monday, Sept. 22, in class or instructor's office by 11:00am. Problem 12 can be skipped - it will not be graded.
Instructor: Peter Petrov, AVW 1421, ppetrov at ece dot umd dot edu
Class hours: MWF 10:00am - 10:50pm, KEB 1110
Office hours: MF 11:00am - 12:00pm, AVW 1421
Required text: "Digital Principles and Design", by D. Givone
Teaching Assistant: Navik Agrawal, navik at umd dot edu
Office hours: W 12:00pm - 1:00pm, Engineering Annex 0305
Final exam : 35%, Saturday, Dec 20, 8:00am - 10:00am, KEB 1110
Synthesis of Synchronous Sequential Networks.
Synchronous Sequential Networks. Analysis.
Registers and Counters
Sequential Networks; Latches
Programmable Logic Devices (PLD)
Comparators, Decoders, Encoders
Binary Adders and Subtractors.
Nand/Nor-only conversion. Gate properties.
Course Work, Policies, and Grading
There will be 3 (three) midterm exams and a final exam. The lowest midterm score will be discarded. The exams will be based entirely on the course readings and will be closed book, closed notes. Before each exam I will assign homework problems, which purpose is to prepare you for the exams. The homework problems will be collected and graded. The lowest homework score will be dropped. The final grade will be formed as follows:
Midterm 1 (September 26, in class) : 25%
Midterm 2 (October 24, in class) : 25%
Midterm 3 (November 24, in class) : 25%
4 Homework assignments: 5% each
Final : 35%, Saturday, Dec 20, 8:00am - 10:00am, KEB 1110