ENEE 206 LABORATORY 2
Synchronous and Asynchronous Counters
Feburuary 3, 2004
A. Lab goals
- The main purpose of this lab is to introduce the basic laboratory procedures necessay to
evaluate simple digital circuits:
- how to convert logic diagrams intocircuit diagrams,
- how to use breadboards to build the circuits and
- how to use an oscilloscope to test the circuit
- Two additinal goals are
- to introduce basic TTL and CMOS chips and
- to learn about the experimental realization of logical zsros and ones.
B. Background Reading
- Read sections 7.3 and 7.4 in Nelson and Nagle(N/N)to review synchronous and
asynchronous counters.
- Make certain that you read the laboratory procedure ahead of time and answer
the Pre-lab questions about the reading.
C. Definitions
- TTL - Transistor-Transistor Logic
- CMOS - Complementary-Metal-Oxide-Semiconductor
- Delay - the time it takes for an input signal state change to affect the output signal
- DIP - Dual in-line package
- Duty Factor - the percentage of the period that the signal is in the "on" state.
- Rise/Fall time - when a signal is changing from "off" to "on", the time it takes
for the signal to go from 10% of the final value to 90% of the final value is Rise Time.
Fall Time refers to transition from "on" to "off".
- Glitch - static timing hazard - when a change in the input produces a momentary output change
(when no change should occur).
- IC - Integrated circuit
- Logic Diagram vs. Wiring Diagram(Fig 2.2) - The logic diagram shows the individual symbols
of the logic elements with their interconnections. The wiring diagram shows the pin connctions
to the logic chips and power and ground connections. The logic diagram is used to understand
how the circuit functions but the wiring diagram is used to actually assembe the circuit.
Many components (resistors, capacitors, etc)look identical in both diagrams.
D. Laboratory Equipment
- breadboard
- dc power supply
- chip tester
E. New Hardware
- a few resistors
- DIP switch
- various ICs
C1
C2
C3 | Color | Number |
|
| Black | 0 |
|
| Brown | 1 |
|
| Red | 2 |
|
| Orange | 3 |
|
| Yellow | 4 |
|
| Green | 5 |
|
| Blue | 6 |
|
| Violet | 7 |
|
| Grey | 8 |
|
| White | 9 |
|
| C4 | None | 20% |
|
| White | 10% |
|
| Gold | 5% |
|
R = C1C2 x 10C3
(+/- C4%) ohms
F. Circuit Analysis
A divide-by 2N asynchronous counter
- can be made by cascading N toggle
flip-flops together, with the output Q of the ith stage connected to the clock of
the i+1th stage.
- All presets, clears. J's and K's are tied to VCC.
- logic diagram
- wiring diagram
- The ideal TTL timing diagram
Divide-by-m counter, where m is NOT a power of 2.
Building a comparator circuit and attaching the comparator output to the flip-flop clears
We need a comparator which outputs a logical zero when the counter output is m,
and logical one otherwise.
The logic diagram for a variable divided-by-m (m ≤ 8) comparator circuit is shwon in Fig. 2.11
We use N exclusive-or gates.
One side of each gate is connected to one of the counter output bits.
The other side is connected to a signal that we can switch between logical zero and one.
The wiring diagram for the 3-bit compatator is shwn in Fig. 2.14.
A synchronous divide-by-8 counter
There are a number of key differences between the synchronous and asynchronous counters.
- The synchronous counter has all the clocks tied to the main clock signal.
- The ith flip-flop is set to toggle on lthe next clock pulse onluy if all
proceeding i-1 stages have Q = 1.
- This is accomplished after the third stage via the insertion of a 2-input AND gate
that ANDs the output Q from the previous stage with the output of the previous AND gate.
- To build a divide-by-m counter, where m is not a power of two, a comparator circuit
similar to the one described above for the asynchrounous counter can be used.
G. Helpful Hints
Read all the hints.
Laboratory 2 Description
Synchronous and Asynchronous Counters
Objective:
To design, construct, and test divide-by-N synchronous and asynchrounus counters.
Available Hardware:
Digital component box - see Appendix G.
Pre-lab preparation
Experimental procedure:
During this experiment, be certain that you:
- Read the post-lab questions CAREFULLY to make sure that you can answer them all. Sometimes
these questions involve making measurements that are not explicitly called for in the
lab procedure.
- Ask the TA questions regarding any procedures about which you are uncertain.
- Turn off all power supplies any time that you make any change to the circuit.
- Do NOT apply more that 5 V to the circuit at any time.
- Arrange your circuit components neatly and in a logical order.
- Compare your breadboards carefully with your circuit diagrams before applying power to
the circuit.
- Coplete the following tasks:
- Part 0 - Power the breadboard
- Part I - Asynchrounous divide-by-8 Counter
- Part II - Asynchronous divide-by-M Counter
- Part III - Synchronous divide-by-8 Counter
- Part IV - Synchronous divide-by-M Counter
- Part V - Synchronous divide-by-8 Counter with Alternate Technology
Post-lab analysis:
Generate a lab report following the sample report available in Appendix A.
Mention any difficulties encountered during the lab.
Describe any results that were unexpected and try to account for the origin of
these results
(i.e. explain what happened).
In ADDTION, answer the following questions.
question 1, ... question 10.
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