# These are the Pattern Graphs for use in ENEE644 project.
# Do not modify this file.

# INVERTOR
# INPUTS: 1
# COST  : 1
NOT
1
1
OUT = NOT(A1)

# 2-input NAND gate
# INPUTS: 2
# COST  : 2
NAND2
2
2
OUT = NAND(A1, A2)

# 3-input NAND gate
# INPUTS: 3
# COST  : 3
NAND3
3
3
T1 = NAND (A1, A2)
T2 = NOT (T1)
OUT = NAND(T2, A3)

# 2-input NOR gate
# INPUTS: 2
# COST: 2
NOR2
2
2
T1 = NOT(A1)
T2 = NOT(A2)
T3 = NAND(T1, T2)
OUT = NOT(T3)


# OAI21
# INPUTS: 3
# COST: 3
OAI21
3
3
T1 = NOT(A1)
T2 = NOT(A2)
T3 = NAND(T1, T2)
OUT = NAND(T3, A3)


# 2-input AND gate
# INPUTS: 2
# COST: 2
AND2
2
2
T1 = NAND(A1, A2)
OUT = NOT(T1)

# Feedthrough
# INPUTS: 1
# COST: 0
FEEDTHRU
1
0
T1 = NOT(A1)
OUT = NOT(T1)

# 3-input AND gate
# INPUTS: 3
# COST: 3
AND3
3
3
T1 = NAND(A1, A2)
T2 = NOT(T1)
T3 = NAND(T2, A3)
OUT = NOT(T3)

# 4-input AND gate.
# 2 patterns
# INPUTS: 4
# COST  : 4
# Note that the second pattern may be tricky.
AND4-1
4
4
T1 = NAND(A1, A2)
T2 = NAND(A3, A4)
T3 = NOT(T1)
T4 = NOT(T2)
T5 = NAND(T3, T4)
OUT = NOT(T5)

AND4-2
4
4
T1 = NAND(T2, A4)
T2 = NOT(T3)
T3 = NAND(T4, A3)
T4 = NOT(T5)
T5 = NAND(A1, A2)
OUT = NOT(T1)

# 4-input NAND GATE
# 2 patterns
# INPUTS: 4
# COST: 4
NAND4-1
4
4
T1 = NAND(A1, A2)
T3 = NAND(A3, A4)
T2 = NOT(T1)
T4 = NOT(T3)
OUT = NAND(T2, T4)

NAND4-2
4
4
T1 = NAND(A1, A2)
T2 = NOT(T1)
T3 = NAND(T2, A3)
T4 = NOT(T3)
OUT = NAND(T4, A4)

# 2-input OR gate
# INPUTS:2
# COST: 2
OR2
2
2
T1 = NOT(A1)
T2 = NOT(A2)
OUT = NAND(T1, T2)

# 3-input OR gate
# INPUTS: 3
# COST: 3
OR3
3
3
T1 = NOT(A1)
T2 = NOT(A2)
T3 = NAND(T1, T2)
T4 = NOT(T3)
T5 = NOT(A3)
OUT = NAND(T4, T5)

# Custom F3
# 2 patterns
# INPUTS: 3
# COST  : 4
F3-1
3
4
T1 = NAND(A1, A2)
T2 = NOT(T1)
T3 = NOT(A3)
T4 = NAND(T2, T3)
OUT = NOT(T4)

F3-2
3
4
T1 = NOT(A1)
T2 = NAND(T1, A2)
T3 = NOT(T2)
T4 = NAND(A3, T3)
OUT = NOT(T4)

# Custom F4
# INPUTS: 4
# COST: 5
F4
4
5
T1 = NAND(A1, A2)
T2 = NOT(A3)
T3 = NOT(A4)
T4 = NAND(T1, T2)
OUT = NAND(T3, T4)