Course Information

Lecture:	Tue Thu 12:30 - 1:45, EGR-1104
Mailing List:	enee446-0201-spr12@coursemail.umd.edu
Required Text:	Jacob, Ng, & Wang, Memory Systems: Cache, DRAM, Disk, Morgan Kaufmann, 2007
Recommended Text:	Hennessy & Patterson, Computer Architecture: A Quantitative Approach, 4th Ed., Morgan Kaufmann
Recommended Text:	Smith & Franzon, Verilog Styles for Syntehsis of Digital Systems, Prentice Hall

Instructor Information

Professor:	Bruce L. Jacob, Electrical & Computer Engineering
Office:	1333 A.V. Williams Building
Phone:	(301) 405-0432
Email:
Office Hours:	Tuesday/Thursday, Open-door policy ...

Teaching Assistant:	Chao Wang
Phone:
Email:	chaowang@umd.edu
Office Hours:	to be determined

Course Handouts and General Information

• Syllabus2012.pdf
• verilog-handbook.pdf. This is a concise overview of the Verilog programming language.
• realize-verilog.pdf. Gives a functional view of Verilog; i.e. if you want to build a processor model, this shows how. However, it confuses blocking/non-blocking assignments (calls "=" non-blocking and "<=" blocking). Otherwise, it is a decent overview.
• IBM 360/91's Out-of-Order Fixed-Point Pipe. Describes (my guess as to) the implementation of instruction enqueue, issue, and commit in the IBM 360/91 fixed-point pipeline. In contrast, the 360/91's floating-point pipeline is famous for its implementation of Tomasulo's algorithm, which is well documented.
• "PC processor microarchitecture." Keith Diefendorff. Microprocessor Report, vol. 13, no. 9, pp. 16-22, July 12 2000.
• A Crash Course in C Programming
• Analysis of Cost and Performance
• "Virtual memory: Issues of implementation." Bruce Jacob and Trevor Mudge. IEEE Computer, vol. 31, no. 6, pp. 33-43. June 1998.
• The OS and Multitasking: An Example

Background on branch prediction

• "A study of branch prediction strategies." Jim Smith. In Proc. 8th Annual International Symposium on Computer Architecture (ISCA), pp. 135-148. Minneapolis MN, May 1981.

  This describes, among other things, the use of adaptive/dynamic state machines (e.g. saturating counters) to track branch behavior and to predict future behavior based on that observed past behavior.

• "Branch prediction strategies and branch target buffer design." Johnny K. F. Lee and Alan Jay Smith. IEEE Computer, vol. 17, no. 1, pp. 6-22. January 1984.

  A nice description of the branch-target buffer and a description of what Yeh & Patt call a "static training" branch prediction scheme in which a branch history (string of bits signifying taken/not-taken status of most recent branch outcomes) is used to generate a prediction. That prediction can be generated by profiling a set of benchmarks. The article also explores a few other adaptive state machines besides saturating counters.

• "Two-level adaptive training branch prediction." Tse-Yu Yeh and Yale N. Patt. In Proc. 24th Annual International Symposium on Microarchitecture (MICRO), pp. 51-61. Albuquerque NM, November 1991.

  Combines the concept of the history-indexed table, as described in Lee & Smith [1984] (called static training by Yeh & Patt) and the use of adaptive state machines, as described in Smith [1981]. Instead of putting a static prediction bit into the table, an adaptive state machine is put into each entry in the table. Note that later papers by Yeh & Patt change the name of the scheme to "two-level adaptive branch prediction" (dropping the "training").

Articles well worth reading

• "The MIPS R10000 superscalar microprocessor." Kenneth C. Yeager. IEEE Micro, vol. 16, no. 2, pp. 28-40, April 1996.

• "Implementing precise interrupts in pipelined processors." James. E. Smith and Andrew. R. Pleszkun. IEEE Transactions on Computers, vol. 37, no. 5, pp. 562-573, May 1988.

• "Dynamic instruction scheduling and the Astronautics ZS-1." James E. Smith. IEEE Computer, vol. 22, no. 7, pp. 21-35, July 1989.

• "An efficient algorithm for exploiting multiple arithmetic units." Robert. M. Tomasulo. IBM Journal of Research and Development, vol. 11, no. 1, pp. 25-33, January 1967.

Assignments

ID	Out	Due	Write-up	Distribution	Updated
Project 1	26 Jan 2012	07 Feb 2012	p1.pdf	Project 1	24 Jan 2012
Project 2	09 Feb 2012	13 Mar 2012	p2.pdf	Project 2	09 Feb 2012
Project 3	15 Mar 2012	01 May 2012	p3.pdf	Project 3	12 Apr 2012

Documents describing the RiSC-16

File Name	Document Name	Document Description
F2002-RiSC-ISA.pdf	The RiSC-16 Instruction-Set Architecture	Describes the instruction-set architecture: machine-code forms, assembly-code forms, etc.
F2002-RiSC-seq.pdf	RiSC-16: Sequential Implementation	Describes a sequential implementation of the architecture: control flow, data flow, etc.
F2002-RiSC-pipe.pdf	The Pipelined RiSC-16	Describes a pipelined implementation of the architecture: control flow, data flow, pipeline stages, pipeline hazards, data forwarding, etc.

Source Code

File Name	Description of Contents
laplace.s	RiSC-16 assembly code for a decent-sized benchmark, written by Vince Weaver and Asher Lazarus -- former enee350 and enee759m students.