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Course Information
| Lecture: | Tue Thu 12:30 - 1:45, EGR-1104 |
| Mailing List: | enee446-0201-spr12@coursemail.umd.edu |
| Required Text: | Jacob, Ng, & Wang, Memory Systems: Cache, DRAM, Disk, Morgan Kaufmann, 2007 |
| Recommended Text: | Hennessy & Patterson, Computer Architecture: A Quantitative Approach, 4th Ed., Morgan Kaufmann |
| Recommended Text: | Smith & Franzon, Verilog Styles for Syntehsis of Digital Systems, Prentice Hall |
Instructor Information
| Professor: | Bruce L. Jacob, Electrical & Computer Engineering |
| Office: | 1333 A.V. Williams Building |
| Phone: | (301) 405-0432 |
| Email: |
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| Office Hours: | Tuesday/Thursday, Open-door policy ... |
| Teaching Assistant: | Chao Wang |
| Phone: | |
| Email: | chaowang@umd.edu |
| Office Hours: | to be determined |
Course Handouts and General Information
Background on branch prediction
This describes, among other things, the use of adaptive/dynamic state machines (e.g. saturating counters) to track branch behavior and to predict future behavior based on that observed past behavior.
A nice description of the branch-target buffer and a description of what Yeh & Patt call a "static training" branch prediction scheme in which a branch history (string of bits signifying taken/not-taken status of most recent branch outcomes) is used to generate a prediction. That prediction can be generated by profiling a set of benchmarks. The article also explores a few other adaptive state machines besides saturating counters.
Combines the concept of the history-indexed table, as described in Lee & Smith [1984] (called static training by Yeh & Patt) and the use of adaptive state machines, as described in Smith [1981]. Instead of putting a static prediction bit into the table, an adaptive state machine is put into each entry in the table. Note that later papers by Yeh & Patt change the name of the scheme to "two-level adaptive branch prediction" (dropping the "training").
Articles well worth reading
Assignments
| ID | Out | Due | Write-up | Distribution | Updated |
| Project 1 | 26 Jan 2012 | 07 Feb 2012 | p1.pdf | Project 1 | 24 Jan 2012 |
| Project 2 | 09 Feb 2012 | 13 Mar 2012 | p2.pdf | Project 2 | 09 Feb 2012 |
| Project 3 | 15 Mar 2012 | 01 May 2012 | p3.pdf | Project 3 | 12 Apr 2012 |
Documents describing the RiSC-16
| File Name | Document Name | Document Description |
| F2002-RiSC-ISA.pdf | The RiSC-16 Instruction-Set Architecture | Describes the instruction-set architecture: machine-code forms, assembly-code forms, etc. |
| F2002-RiSC-seq.pdf | RiSC-16: Sequential Implementation | Describes a sequential implementation of the architecture: control flow, data flow, etc. |
| F2002-RiSC-pipe.pdf | The Pipelined RiSC-16 | Describes a pipelined implementation of the architecture: control flow, data flow, pipeline stages, pipeline hazards, data forwarding, etc. |
Source Code
| File Name | Description of Contents |
| laplace.s | RiSC-16 assembly code for a decent-sized benchmark, written by Vince Weaver and Asher Lazarus -- former enee350 and enee759m students. |