(easy)
1.) A compiler designer is trying to decide between 2 code sequences for a particular machine. The following is given:

Instruction type	CPI
A	1
B	2
C	3

For a particular high-level statement, the compiler writer is considering 2 code sequences that require the following instruction counts (IC):

code sequence	A	B	C
*1	2	1	2
*2	4	1	1

Which code sequence executes the least instructions? Which will be faster? What is CPI for each sequence?

(medium)
2.) You are a computer designer. Your study of usage of high-level language constructs suggests that procedure calls are one of the most expensive operation. You have invented a scheme that reduces the loads and stores normally associated with procedure calls and returns. The first thing you do is run some experiments with and without this optimization. Your experiments use the same state-of-the-art optimizing compiler that will be used with either version of the computer. These experiments reveals the following information:

- The clock rate of the unoptimized version is 5% higher.

- 30% of the instructions in the unoptimized version are loads or stores.

- The optimized version executes two-thirds (2/3) as many loads and stores as the unoptimized version. For all other instructions, the dynamic execution counts are unchanged.

- All instructions (including load and store) take one clock cycle.

Which is faster? Justify your answer quantitatively.

(hard)
3.) Suppose we are considering a change to an instruction set. The base machine initially has only loads and stores to memory, and all operations work on the registers. Such machines are called load-store machine. Measurements of the load-store machine showing instruction mix and clock cycles count per instruction are given:

Instruction type	Frequency	Clock cycle count
ALU ops	43%	1
Loads	21%	2
Stores	12%	2
Branches	24%	2

Let's assume that 25% of the ALU operations directly use a loaded operand that is not used again.

We propose adding ALU instructions that have one source operand in memory. These new register-memory instructions have a clock cycle count of 2. Suppose that the extended instruction set increases the clock cycle count for branches by 1, but it does not affect the clock cycle time. Would this change improve CPU performance?


Note: Homework problems are also good practice problems.









Prepared by Quang Trinh, October 30, 2002.