ENEE 244 - Digital Logic Design

(Sections 101-104)

Spring 2006

**Midterm I syllabus:**

Chapter 1: (not in syllabus)

Chapter 2: 2.1, 2.2, 2.3 (except 2.3.4), 2.4, 2.5 (except 2.5.2 and 2.5.4), 2.6. 2.7, 2.8, 2.10 (only codes covered in class), 2.11.

Chapter 3: 3.1, 3.2, 3.3, 3.4, 3.5, 3.6 (except 3.6.2 and 3.6.4), 3.7,
3.8, 3.9 (except 3.9.4 and 3.9.5).

(our presentation of sections 3.1 to 3.3 differs significantly from that in the
book. We start with section 3.3 and derive the theorems in 3.1 and 3.2
from the truth tables, which is a lot easier than the theoretical derivations in
the book.)

**Midterm II syllabus:**

Chapter 4: 4.1, 4.2 (except proofs of theorems), 4.3, 4.4, 4.5, 4.6, 4.7* (except 4.7.2).

* = for 5-variable K-maps, we used the layer structure K-map in the lecture, not the reflective structure K-map in the book.

Chapter 5: 5.1, 5.3, 5.4, 5.5, 5.6**.

** = In section 5.6.1, only the first two pages are in syllabus. The rest on implemented n-variable K-maps with a 2

^{n-1 }to 1 MUX is not in syllabus.

Chapter 6: 6.1, 6.2 (except 6.2.2), 6.4 (6.4.1 only).

**Portion after Midterm II:*** //The final
exam is on material from the entire course.*

Chapter 6: 6.4, 6.5 (except 6.5.5), 6.6. // Rest of chapter 6 is covered after chapter 7.

Chapter 7: 7.1, 7.2, 7.3 (cover examples on your own), 7.5 (excluding 7.5.1), 7.6 (excluding 7.6.1).

Chapter 6 [return to chapter 6]: 6.7, 6.8, 6.9.

*-- Although unlikely, there may be more material here if time permits. --*