Outline of topics
(subject to revision by instructor)
ENEE 244 - Digital Logic Design
(Sections 201-206)
Spring 2002



1. Binary Numbers; binary arithmetic and codes (Chapt.1)
2. Boolean Algebra, switching algebra, and logic gates (Chapt. 2)
3. Karnaugh Maps, simplification of Boolean functions (Chapt. 3)
4. Combinational Design; NAND/NOR implementation (Chapt. 3)

Midterm exam I (Exact date will be announced in class.)

5. Combinational Logic Design: adders, subtracters, multipliers, comparators, decoders, encoders and multiplexers. (Chapt. 4)
6. Latches and flip- flops (Chapt. 5)
7. Synchronous sequential circuit design and analysis (Chapt. 5)
8. Registers, synchronous and asynchronous counters. (Chapt. 6)
9. Memories (Chapt. 7)

Midterm exam II (Exact date will be announced in class.)

10. RTL level: ASM charts, Control Logic Design (Chapt. 8)
11. Wired logic and characteristics of logic gate families (Chapt. 10)

Final Exam (Firm date; see course information)
 

Optional Topics as time permits:

1. State Reduction and Good State Variable Assignments (Chapt. 5)