Kim Lecture Hall, Rm. 1110
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Booz Allen Hamilton Distinguished Colloquium in Electrical and Computer Engineering:
"Can a PRAM-on-Chip Vision Save the Software Spiral?"
Dr. Uzi Vishkin
Professor, Computer Engineering, University of Maryland
September 19, 2008, 2:00 p.m.
Jeong H. Kim Engineering Building, Rm. 1110
General-purpose computing is one of the biggest success stories of technology as a business model. Intel’s former CEO, Andy Grove, observed that the software spiral (where improvement in hardware leads to improvement in software that leads back to improvement in hardware) has been a powerful engine of sustained growth for information technology (IT). Keeping general-purpose computing on track now, that it needs to be reinvented for parallelism (especially for reducing single-task completion time), is one of the biggest challenges of our times. Failing to do that can cause a recession in the IT sector, since software productivity problems are breaking the spiral. The lead core competence of our approach is our understanding of parallel algorithmic thinking and parallel programming. This competence forms the basis for remedying the software productivity breakdown of the spiral through a massively parallel on-chip architecture. The approach reflects a grand vision where parallel computing becomes mainstream and is incorporated in the processor-of-the-future. However, it is important to remember that vision is not enough: the devil is in the details.
The PRAM-On-Chip project started at UMD in 1997 foreseeing this spiral breakdown challenge and opportunity. Building on PRAM – a parallel algorithmic approach that has never been seriously challenged on ease of thinking, or wealth of its knowledge-base – a comprehensive and coherent platform for on-chip general-purpose parallel computing has been developed and prototyped. Optimizing single-task completion time, the platform accounts for application programming (VHDL/Verilog, OpenGL, MATLAB, etc), parallel algorithms, parallel programming, compiling, architecture and deep-submicron implementation, as well as backwards compatibility on serial code. The approach goes after any type of application parallelism regardless of its amount, regularity, or grain size. Some prototyping highlights include: an eXplicit Multi-Threaded (XMT) architecture, a new 64-processor, 75MHz XMT (FPGA-based) computer, 90nm ASIC tape-outs, a basic compiler, class tested programming methodology where (even high-school) students are taught only parallel algorithms and pick the rest on their own, and up to 100X speedups on applications. The talk will conclude by arguing that the PRAM-On-Chip approach is a promising candidate for providing the processor-of-the-future.
Uzi Vishkin got his DSc degree from the Technion, Israel in 1981. He has been a Professor of Electrical and Computer Engineering and a permanent member of the University of Maryland Institute for Advanced Computer Studies (UMIACS) since 1988. He has held academic positions at New York University, Tel Aviv University (where he was Chair of Computer Science) and the Technion. His work-depth methodology for presenting parallel algorithms provided the presentation framework in several parallel algorithm texts that also include quite a few of his parallel algorithms. He is the inventor of the PRAM-On-Chip desktop supercomputer framework under development since 1997 at UMD. He was elected ACM Fellow in 1996 for, among other things, having “played a leading role in forming and shaping what thinking in parallel has come to mean in the fundamental theory of Computer Science”, is an ISI-Thompson Highly Cited Researcher and was named a Maryland 2007 Innovator of the Year for his PRAM-On-Chip venture.
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