FDI-SRP Project Publications

A BibTeX file containing bibliographic information for all publications listed here is also available.

Globally, this publication list is ordered in reverse chronological order. Within a given year, the ordering is alphabetical (by author name).

The primary sponsor of the DSPCAD Group's work in this research area is: the U.S. National Science Foundation. We are also grateful to the following sponsors, who have supported the research in Maryland DSPCAD Research Group at large: Agilent Technologies; Angeles Design Systems, Inc.; CoolCAD Electronics; the Defense Advanced Research Projects Agency; the Department of Homeland Security; the Laboratory for Physical Sciences; the Laboratory for Telecommuniation Sciences; Management Communications and Control, Inc.; the Maryland Industrial Partnerships (MIPS) Program; National Instruments; the National Radio Astronomy Obervatory; Northrop Grumman Corp.; the Semiconductor Research Corporation; Techno-Sciences, Inc.; Texas Instruments, Inc.; Trident Systems, Inc.; the University of Maryland Graduate School; the US Air Force Research Laboratory; the US Army Research Laboratory; the US Army Research Office; and the US National Science Foundation.

Any opinions, findings and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the project sponsor(s).

People in the Maryland DSPCAD Research Group.

[bhat2011x2]

S. S. Bhattacharyya, W. Plishker, N. Sane, C. Shen, and H. Wu. Modeling and optimization of dynamic signal processing in resource-aware sensor networks. In Proceedings of the Workshop on Resources Aware Sensor and Surveillance Networks in conjunction with IEEE International Conference on Advanced Video and Signal-Based Surveillance, pages 449-454, Klagenfurt, Austria, August 2011. (PDF)

[kee2011x1]

H. Kee, C. Shen, S. S. Bhattacharyya, I. Wong, Y. Rao, and J. Kornerup. Mapping parameterized cyclo-static dataflow graphs onto configurable hardware. Journal of Signal Processing Systems, 2011. DOI: DOI 10.1007/s11265-011-0599-5. (PDF)

[lee2011x2]

D. Lee, M. Wolf, and S. S. Bhattacharyya. High-performance and low-energy buffer mapping method for multiprocessor DSP systems. ACM Transactions on Embedded Computing Systems, 2011. To appear.

[sane2011x2]

N. Sane. Rapid Prototyping of High Performance Signal Processing Applications. PhD thesis, Department of Electrical and Computer Engineering, University of Maryland, College Park, 2011. (PDF)

[shen2011x2]

C. Shen, W. Plishker, and S. S. Bhattacharyya. Dataflow-based design and implementation of image processing applications. In L. Guan, Y. He, and S-Y. Kung, editors, Multimedia Image and Video Processing. CRC Press, second edition, 2011. To appear.

[shen2011x3]

C. Shen, W. Plishker, and S. S. Bhattacharyya. Dataflow-based design and implementation of image processing applications. Technical Report UMIACS-TR-2011-11, Institute for Advanced Computer Studies, University of Maryland at College Park, 2011. http://drum.lib.umd.edu/handle/1903/11403. (PDF)

[shen2011x4]

C. Shen, L. Wang, I. Cho, S. Kim, S. Won, W. Plishker, and S. S. Bhattacharyya. The DSPCAD lightweight dataflow environment: Introduction to LIDE version 0.1. Technical Report UMIACS-TR-2011-17, Institute for Advanced Computer Studies, University of Maryland at College Park, 2011.

[wu2011x2]

S. Wu. Representation and scheduling of scalable dataflow graph topologies. Master's thesis, Department of Electrical and Computer Engineering, University of Maryland, College Park, 2011. (PDF)

[bhat2010x3]

S. S. Bhattacharyya, E. F. Deprettere, and J. Keinert. Dynamic and multidimensional dataflow graphs. In S. S. Bhattacharyya, E. F. Deprettere, R. Leupers, and J. Takala, editors, Handbook of Signal Processing Systems, pages 899-930. Springer, 2010. (PDF)

[chen2010x1]

Y-K Chen, C. Chakrabarti, S. Bhattacharyya, and B. Bougard. Signal processing on platforms with multiple cores: Part 2 --- design and applications. IEEE Signal Processing Magazine, 27(2):20-21, March 2010. Guest Editors' Introduction. (PDF)

[kee2010x2]

H. Kee. Systematic Exploration of Trade-offs between Application Throughput and Hardware Resource Requirements in DSP Systems. PhD thesis, Department of Electrical and Computer Engineering, University of Maryland, College Park, 2010. (PDF)

[kee2010x3]

H. Kee, S. S. Bhattacharyya, and J. Kornerup. Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, pages 136-143, Samos, Greece, July 2010. (PDF)

[kee2010x1]

H. Kee, I. Wong, Y. Rao, and S. S. Bhattacharyya. FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous dataflow techniques. In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, pages 1510-1513, Dallas, Texas, March 2010. (PDF)

[sane2010x3]

N. Sane, H. Kee, G. Seetharaman, and S. S. Bhattacharyya. Scalable representation of dataflow graph structures using topological patterns. In Proceedings of the IEEE Workshop on Signal Processing Systems, pages 13-18, San Francisco Bay Area, USA, October 2010. (PDF)

[shen2010x2]

C. Shen, W. Plishker, H. Wu, and S. S. Bhattacharyya. A lightweight dataflow approach for design and implementation of SDR systems. In Proceedings of the Wireless Innovation Conference and Product Exposition, pages 640-645, Washington DC, USA, November 2010. (PDF)

[wu2010x1]

H. Wu, H. Kee, N. Sane, W. Plishker, and S. S. Bhattacharyya. Rapid prototyping for digital signal processing systems using parameterized synchronous dataflow graphs. In Proceedings of the International Symposium on Rapid System Prototyping, pages 1-7, Fairfax, Virginia, June 2010. (PDF)

[wu2010x2]

H. Wu, C. Shen, S. S. Bhattacharyya, K. Compton, M. Schulte, M. Wolf, and T. Zhang. Design and implementation of real-time signal processing applications on heterogeneous multiprocessor arrays. In Proceedings of the IEEE Asilomar Conference on Signals, Systems, and Computers, pages 2121-2125, Pacific Grove, California, November 2010. Invited paper. (PDF)

[chen2009x3]

Y-K Chen, C. Chakrabarti, S. Bhattacharyya, and B. Bougard. Signal processing on platforms with multiple cores: Part 1 --- overview and methodologies. IEEE Signal Processing Magazine, 26(6):24-25, November 2009. Guest Editors' Introduction. (PDF)

[lee2009x1]

D. Lee, S. S. Bhattacharyya, and W. Wolf. High-performance buffer mapping to exploit DRAM concurrency in multiprocessor DSP systems. In Proceedings of the International Symposium on Rapid System Prototyping, pages 137-144, Paris, France, June 2009. (PDF)

[bhat2008x2]

S. S. Bhattacharyya, G. Brebner, J. Eker, J. W. Janneck, M. Mattavelli, and M. Raulet. How to make stream processing more mainstream. In Proceedings of the Workshop on Streaming Systems, Lake Como, Italy, November 2008. 3 pages. (PDF)

[bhat2008x4]

S. S. Bhattacharyya, G. Brebner, J. Eker, J. W. Janneck, M. Mattavelli, C. von Platen, and M. Raulet. OpenDF --- a dataflow toolset for reconfigurable hardware and multicore systems. In Proceedings of the Swedish Workshop on Multi-Core Computing, pages 43-49, Ronneby, Sweden, November 2008. (PDF)

[plis2008x1]

W. Plishker, N. Sane, M. Kiemb, K. Anand, and S. S. Bhattacharyya. Functional DIF for rapid prototyping. In Proceedings of the International Symposium on Rapid System Prototyping, pages 17-23, Monterey, California, June 2008. (PDF)

[plis2008x2]

W. Plishker, N. Sane, M. Kiemb, and S. S. Bhattacharyya. Heterogeneous design in functional DIF. In Proceedings of the International Workshop on Systems, Architectures, Modeling, and Simulation, pages 157-166, Samos, Greece, July 2008. (PDF)

[plis2010x1]

W. Plishker, N. Sane, M. Kiemb, and S. S. Bhattacharyya. Heterogeneous design in functional DIF. Transactions on High-Performance Embedded Architectures and Compilers. Online version available from http://www.hipeac.net/node/3030, print version to appear. (PDF)

[sane2011x1]

N. Sane, H. Kee, G. Seetharaman, and S. S. Bhattacharyya. Topological patterns for scalable representation and analysis of dataflow graphs. Journal of Signal Processing Systems. Online version published (DOI: 10.1007/s11265-011-0610-1), print version to appear.