ENEE 759T: Challenges in Automated System Design Methodologies

Course Goals:

Integrated system design is an ever evolving process, with improving fabrication technologies (sub micro, nano meter), new design and computational paradigms and new applications (embedded, high performance, low power, network, bio). Such dynamics and evolution pose new challenges to system designers and specifically VLSI CAD tool developers. Working around these new problems is the only way to keep pace with ever increasing appetite for better and faster electronic systems in our lives. Specifically, this course will first overview with the modern challenges and issues in effective system design methodologies. Some of these challenges include power estimation/optimization in modern embedded systems, methodologies for Power Management in all sections of the chip, effects of deepsubmicron technologies on current CAD techniques, optimization of delay, clock frequency, noise, congestion and chip area. All this will be reviewed mostly from a high level point of view with stress of algorithms and heuristics. This will be followed by a study of alternate design methodologies that should be used in order to address the new challenges.

Course Prerequisite(s):

ENEE 644, ENEE 641, Permission from the Instructor

Topics Prerequisite(s):

Basic VLSI Design and CAD, Basic Algorithms, Basic Graph theory, Very Basic Probability Theory

Textbook(s)

None

Reference(s):

N. Weste and K. Eshraghian, `Principles of CMOS VLSI Design: A Systems Perspective', 2nd Edition, Addison-Wesley Publishers

J. M. Rabaey and M. Pedram (eds.), `Low Power Design Methodologies,' Kluwer Academic Publishers, 1996.

G. De Miocheli, Synthesis and Optimization of Digital Circuits, Mc Graw Hill

Current Research Papers

Core Topics:

• Power Optimization Estimation
• Power Mangement
• Integration of Physical Design and Synthesis/ Single Iteration Design Flow
• Deep Submicron Issues from a CAD perspective

Optional Topics:

• Nanotechnology
• Bio computing, DNA computing

Course Structure:

Grading Method: