ENEE 750: VLSI Design Automation

Course Description

Computer-Aided Design (CAD) tools play a key role in the development of microelectronic systems such as microprocessor and DSP chips. We study techniques to develop such CAD tools so as to automate the design process of VLSI circuits and systems. Many of these techniques are also applicable to Printed Circuit Board (PCB) design. We examine fully the physical layout aspect of VLSI design automation such as partitioning, floorplanning, placement, global and detailed routing. We also consider state-of-the-art CAD issues such as implementation of VLSI systems with Field Programmable Gate Arrays (FPGAs) and Multi-Chip Modules (MCMs). If time permits, other aspects of VLSI design automation will be covered.

CAD tool design and development projects will be assigned. New CAD tools will be integrated into existing CAD tool sets. Real-world chip designs will then be used to generate their mask layouts, which will be sent to MOSIS for chip fabrication.

Course Prerequisite:

Basic knowledge of data structures (e.g., arrays, linked lists, queues, stacks, binary trees). and algorithms. For further knowledge, consult any book on such subjects. relevant background material.

Textbook:

N. Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Publishers, 1993.

References:

  1. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., Addison-Wesley, 1992.
  2. W. Wolf, Modern VLSI Design, Prentice-Hall, 1994.

Core Outline:

  1. Overview of VLSI Design
    • VLSI Design Cycle
    • VLSI Design Styles
    • System Packaging Styles
    • VLSI CAD Tools
  2. Design and Fabrication of VLSI Devices
    • Fabrication of VLSI Circuits
    • Design Rules
  3. Data Structures and Basic Algorithms
    • Complexity Issues
    • Basic Algorithms
    • Basic Data Structures
    • Graph Algorithms for VLSI Physical Design
  4. Partitioning
    • Group Migration Methods
    • Simulated Annealing Approach
    • Performance Driven Partitioning
  5. Placement, Floorplanning, and Pin Assignment
  6. Global Routing
    • Maze Routing
    • Line Search
    • Shortest Path Based Methods
    • Steiner Tree Based Methods
  7. Detailed Routing
    • Single-Layer Routing
    • Two-Layer Channel Routing
    • Three-Layer Channel Routing
    • Switch-box Routing
  8. Via Minimization and Over-the-Cell Routing
  9. Specialized Routing
    • Clock Routing
    • Power and Ground Routing
  10. Layout Compaction
    • One-Dimensional Compaction
    • Virtual Grid Based Compaction
    • Two-Dimensional Compaction
  11. Physical Design Automation of FPGAs
  12. Physical Design Automation of MCMs

Course Requirements:

  • Homework Assignments (and midterm exam, if needed): 60-70%
  • Final Project, Presentation, and Report: 30-40%
Note: This course can be taken concurrently with ENEE 644 Computer-Aided Design of Digital Systems and ENEE 648T VLSI Architecture. Knowledge of and experience with VLSI design using CAD tools (e.g., MAGIC, OCTTOOLS, PARTHENON, VHDL) provide a stronger motivation to learn the subjects of this course, but they are not essential. The first two chapters of the textbook cover relevant background material.

Last Updated:

Spring 1995 by Professors Kazuo Nakajima and Shinji Nakamura