ENEE 646: Digital Computer Design

Course Goals:

Concepts and techniques for design of computer systems with improved performance. Advanced I/O systems, memory organization, pipelined and parallel processors, processor/memory interconnections, bus bandwidth, cache memory, virtual memory, multiprocessors, performance evaluation.

Course Prerequisites:

ENEE 446 or equivalent.

Topics Prerequisites:

Basic understanding and knowledge of basic digital computer design including processor, memory, and I/O organization and interconnections and instruction set architecture. The student is expected to have basic knowledge and experience in assembly language programming for at least one instruction set architecture. Basic probability theory is required for performance evaluation.

References:

  1. D. A. Patterson and J. L. Hennessy, Computer Architecture - A Quantitative Approach, (second edition), Morgan Kaufmann Publishers, San Francisco, California, 1996.
  2. Kai Hwang, Advanced Computer Architecture - Parallelism, Scalability, Programmability, McGraw-Hill, New York, 1993.
  3. J. L. Hennessy and D.A. Patterson, Computer Organization & Design - The hardware/software interface, Morgan Kaufmann Publishers, San Francisco, California, 1994.

Core Topics:

  • Instruction set design including classification of instruction sets, instruction formats, operand types, sizes, and memory addressing, and examples of the DLX architecture.
  • Control subsystem design including processor datapaths, instruction execution steps, hardwired vs. microprogrammed control, interrupt handling, microprogram optimization.
  • Pipelining and parallelism including: principles of overlapped instruction execution, pipeline hazards, structural, data, and control hazards examples and handling; exception handling and instruction restart, static and dynamic pipeline scheduling, pipeline schedule optimization, branch prediction and penalty reduction. Instruction-level parallelism and multiple instruction issue.
  • Memory-hierarchy design including: cache memory organization, cache access optimizations: reduction of misses, miss penalty, and hit time; cache coherence and cache consistency models; memory organization and bandwidth computation models; memory interleaving; virtual memory, fast address translation, memory protection.
  • Interconnection networks design including: interconnections of processors and memories; shared vs. switched interconnection media; bus bandwidth computation; network properties and routing; switch topology: crossbar, omega, banyan and other networks.
  • Multiprocessor architectures with shared memory vs. distributed local memory, synchronization: locking, barrier synchronization, spin locks; models of memory consistency; performance of multiprocessor systems.

    Optional Topics:

  • Advanced topics on parallel architectures including: hardware support for instruction-level parallelism; program-level parallelism, program partitioning and scheduling; static multiprocessor scheduling; performance metrics for program parallelism.
  • Secondary storage devices including: device interconnections with CPUs and memories, bus design; disk organization and access time computation; performance modeling of disk access; RAID, disk reliability.
  • Networks and network topologies including: routers and gateways; local area networks: rings and ethernets, introduction to asynchronous transfer mode.
  • Computer arithmetic design including: Integer arithmetic: ripple-carry, carry lookahead, carry skip and carry select addition, radix-2 multiplication and division; floating point number representation, the IEEE standard 754; floating point addition, multiplication, and division; multiple precision and exception handling. Pipelining integer and floating-point arithmetic operations.

    Reading List

  • Instruction Set Design. Classification of instruction sets; instruction formats; operand types, sizes, and memory addressing; the DLX architecture. Reference (1), Chapter 2 - all except section 2.7
  • Control Subsystem Design. Processor datapaths; instruction execution steps; hardwired vs. microprogrammed control; interrupt handling; microprogram optimization. Reference (3), Chapter 5 - The Processor: Datapath and Control; sections 5.1-5.7 Reference (3), Appendix C
  • Pipelining and Parallelism. Principles of overlapped instruction execution; pipeline hazards: structural, data, and control hazards examples and handling; exception handling and instruction restart; static and dynamic pipeline scheduling; pipeline schedule optimization; branch prediction and penalty reduction. Instruction-level parallelism and multiple instruction issue; hardware support for instruction-level parallelism; program-level parallelism, program partitioning and scheduling; static multiprocessor scheduling; performance metrics for program parallelism. Reference (1), Chapter 3 - all Reference (1), Chapter 4 - all Reference (2), Chapter 2 - Sections 2.1 - 2.2 Reference (2), Chapter 3 - Section 3.1 Reference (2), Chapter 6 - Sections 6.1 - 6.2
  • Memory-Hierarchy and Storage-System Design. Cache memory organization; cache access optimizations: reduction of misses, miss penalty, and hit time; cache coherence and cache consistency models; memory organization and bandwidth computation models; memory interleaving; virtual memory, fast address translation, memory protection. Secondary storage devices; device interconnections with CPUs and memories, bus design; disk organization and access time computation; RAID, disk reliability. Reference (2), Chapter 4 - Section 4.4 Reference (1), Chapter 5 - 5.3 - 5.11 Reference (1), Chapter 6 - all except section 6.8 and 6.4
  • Interconnection Networks. Interconnections of processors and memories; shared vs. switched interconnection media; network properties and routing; switch topology: crossbar, omega, banyan and other networks; routers and gateways; local area networks; rings and ethernets. Reference (1), Chapter 7 - Sections 7.1 - 7.8 Reference (2), Chapter 2 - Section 2.4 Reference (2), Chapter 7 - Section 7.1
  • Multiprocessors. Multiprocessor architectures with shared memory vs. distributed local memory; synchronization: locking, barrier synchronization, spin locks; models of memory consistency; performance of multiprocessor systems. Reference (1), Chapter 8 - all Reference (1), Appendix E
  • Computer Arithmetic. Integer arithmetic: ripple-carry, carry lookahead, carry skip and carry select addition, radix-2 multiplication and division; floating point number representation, the IEEE standard 754; floating point addition, multiplication, and division; multiple precision and exception handling. Pipelining integer and floating-point arithmetic operations. Reference (3), Chapter 4 - Sections 4.3 - 4.8 OR Reference (1), Appendix A - Sections A.1 - A.7 AND Reference (2), Chapter 6 - Section 6.4

    Comments:

    Students in sections of this course can fabricate VLSI chips via MOSIS.