ENEE:640 VLSI Architecture
The course will cover the most important methodologies for designing custom or semi-custom VLSI systems for a wide variety of applications focusing on some typical signal processing applications. General techniques covered include pipelining, retiming, folding and unfolding, and systolic array design. Mapping of algorithms on array structures, DSP systems, and Field Programmable Gate Arrays (FPGAs) will be described for selected algorithms.
ENEE 446 or equivalent and ENEE 488Z or equivalent; and basic signal processing concepts.
Logic Design, computer architecture, VLSI design, and basic concepts in digital signal processing algorithms.
VLSI Digital Signal Processing Systems, Design and Implementation, Keshab K. Parhi, John Wiley, 1999.
- S. Y. Kung, VLSI Array Processors, Prentice-Hall, 1988.
- W. Wolf, Modern VLSI Design, Prentice-Hall, 1994
- Typical Signal Processing Algorithms
- Overview of VLSI Architectures
- Representations of DSP Algorithms
- General Techniques
- Iteration Bound
- Parallel Processing
- Retiming Techniques
- Definitions and Properties
- General Methodology
- Unfolding and Folding Techniques
- Unfolding Algorithm
- Critical Path, Unfolding, and Retiming
- Folding Transformation
- Register Minimization
- Systolic Architectures
- Design Methodology
- Matrix Operations and 2D Systolic Array Design
- Mapping Algorithms onto Array Structures
- Parallel Algorithm Expressions
- Canonical Mapping Methodology
- Generalized Mapping
- Integer Arithmetic on Arrays
- Carry-Lookahead Addition
- Prefix Computations
- Carry-Save Addition
- Multiplication and Convolution
- Programmable Signal Processors
- Important Features
- DSP Processors for Mobile and Wireless Communications
- Processors for Multidimensional Signal Processing
- One Midterm Exam: 30%
- Assignments: 30%
- Project and Presentation: 40%